Commit b8481381 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.10-2-2024-06-09' of... 

Merge tag 'perf-tools-fixes-for-v6.10-2-2024-06-09' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Arnaldo Carvalho de Melo:

 - Update copies of kernel headers, which resulted in support for the
   new 'mseal' syscall, SUBVOL statx return mask bit, RISC-V and PPC
   prctls, fcntl's DUPFD_QUERY, POSTED_MSI_NOTIFICATION IRQ vector,
   'map_shadow_stack' syscall for x86-32.

 - Revert perf.data record memory allocation optimization that ended up
   causing a regression, work is being done to re-introduce it in the
   next merge window.

 - Fix handling of minimal vmlinux.h file used with BPF's CO-RE when
   interrupting the build.

* tag 'perf-tools-fixes-for-v6.10-2-2024-06-09' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  perf bpf: Fix handling of minimal vmlinux.h file when interrupting the build
  Revert "perf record: Reduce memory for recording PERF_RECORD_LOST_SAMPLES event"
  tools headers arm64: Sync arm64's cputype.h with the kernel sources
  tools headers uapi: Sync linux/stat.h with the kernel sources to pick STATX_SUBVOL
  tools headers UAPI: Update i915_drm.h with the kernel sources
  tools headers UAPI: Sync kvm headers with the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  tools headers: Update the syscall tables and unistd.h, mostly to support the new 'mseal' syscall
  perf trace beauty: Update the arch/x86/include/asm/irq_vectors.h copy with the kernel sources to pick POSTED_MSI_NOTIFICATION
  perf beauty: Update copy of linux/socket.h with the kernel sources
  tools headers UAPI: Sync fcntl.h with the kernel sources to pick F_DUPFD_QUERY
  tools headers UAPI: Sync linux/prctl.h with the kernel sources
  tools include UAPI: Sync linux/stat.h with the kernel sources
parents 637c2dfc ca968082

tools/arch/arm64/include/asm/cputype.h

+6 −0
Original line number Diff line number Diff line
@@ -86,6 +86,9 @@ 
#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B

#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3	0xD84



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -159,6 +162,9 @@ 
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

tools/arch/x86/include/asm/msr-index.h

+4 −5
Original line number Diff line number Diff line
@@ -170,6 +170,10 @@ 
						 * CPU is not affected by Branch

						 * History Injection.

						 */

#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR

						 * supported

						 */

#define ARCH_CAP_PBRSB_NO		BIT(24)	/*

						 * Not susceptible to Post-Barrier

						 * Return Stack Buffer Predictions.
@@ -192,11 +196,6 @@ 
						 * File.

						 */



#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR

						 * supported

						 */



#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			BIT(0)	/*

						 * Writeback and invalidate the

tools/arch/x86/include/uapi/asm/kvm.h

+20 −2
Original line number Diff line number Diff line
@@ -457,9 +457,14 @@ struct kvm_sync_regs { 


#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE	0x00000001



/* attributes for system fd (group 0) */

/* vendor-independent attributes for system fd (group 0) */

#define KVM_X86_GRP_SYSTEM		0

#  define KVM_X86_XCOMP_GUEST_SUPP	0



/* vendor-specific groups and attributes for system fd */

#define KVM_X86_GRP_SEV			1

#  define KVM_X86_SEV_VMSA_FEATURES	0



struct kvm_vmx_nested_state_data {

	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];

	__u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
@@ -689,6 +694,9 @@ enum sev_cmd_id { 
	/* Guest Migration Extension */

	KVM_SEV_SEND_CANCEL,



	/* Second time is the charm; improved versions of the above ioctls.  */

	KVM_SEV_INIT2,



	KVM_SEV_NR_MAX,

};
@@ -700,6 +708,14 @@ struct kvm_sev_cmd { 
	__u32 sev_fd;

};



struct kvm_sev_init {

	__u64 vmsa_features;

	__u32 flags;

	__u16 ghcb_version;

	__u16 pad1;

	__u32 pad2[8];

};



struct kvm_sev_launch_start {

	__u32 handle;

	__u32 policy;
@@ -856,5 +872,7 @@ struct kvm_hyperv_eventfd { 


#define KVM_X86_DEFAULT_VM	0

#define KVM_X86_SW_PROTECTED_VM	1

#define KVM_X86_SEV_VM		2

#define KVM_X86_SEV_ES_VM	3



#endif /* _ASM_X86_KVM_H */

tools/include/uapi/asm-generic/unistd.h

+4 −1
Original line number Diff line number Diff line
@@ -842,8 +842,11 @@ __SYSCALL(__NR_lsm_set_self_attr, sys_lsm_set_self_attr) 
#define __NR_lsm_list_modules 461

__SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)



#define __NR_mseal 462

__SYSCALL(__NR_mseal, sys_mseal)



#undef __NR_syscalls

#define __NR_syscalls 462

#define __NR_syscalls 463



/*

 * 32 bit systems traditionally used different

tools/include/uapi/drm/i915_drm.h

+28 −3
Original line number Diff line number Diff line
@@ -806,6 +806,12 @@ typedef struct drm_i915_irq_wait { 
 */

#define I915_PARAM_PXP_STATUS		 58



/*

 * Query if kernel allows marking a context to send a Freq hint to SLPC. This

 * will enable use of the strategies allowed by the SLPC algorithm.

 */

#define I915_PARAM_HAS_CONTEXT_FREQ_HINT	59



/* Must be kept compact -- no holes and well documented */



/**
@@ -2148,6 +2154,15 @@ struct drm_i915_gem_context_param { 
 * -EIO: The firmware did not succeed in creating the protected context.

 */

#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd



/*

 * I915_CONTEXT_PARAM_LOW_LATENCY:

 *

 * Mark this context as a low latency workload which requires aggressive GT

 * frequency scaling. Use I915_PARAM_HAS_CONTEXT_FREQ_HINT to check if the kernel

 * supports this per context flag.

 */

#define I915_CONTEXT_PARAM_LOW_LATENCY		0xe

/* Must be kept compact -- no holes and well documented */



	/** @value: Context parameter value to be set or queried */
@@ -2623,19 +2638,29 @@ struct drm_i915_reg_read { 
 *

 */



/*

 * struct drm_i915_reset_stats - Return global reset and other context stats

 *

 * Driver keeps few stats for each contexts and also global reset count.

 * This struct can be used to query those stats.

 */

struct drm_i915_reset_stats {

	/** @ctx_id: ID of the requested context */

	__u32 ctx_id;



	/** @flags: MBZ */

	__u32 flags;



	/* All resets since boot/module reload, for all contexts */

	/** @reset_count: All resets since boot/module reload, for all contexts */

	__u32 reset_count;



	/* Number of batches lost when active in GPU, for this context */

	/** @batch_active: Number of batches lost when active in GPU, for this context */

	__u32 batch_active;



	/* Number of batches lost pending for execution, for this context */

	/** @batch_pending: Number of batches lost pending for execution, for this context */

	__u32 batch_pending;



	/** @pad: MBZ */

	__u32 pad;

};