Commit b887afb9 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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dt-bindings: clock: add SM6350 QCOM video clock bindings



Add device tree bindings for video clock controller for SM6350 SoCs.

Signed-off-by: default avatarKonrad Dybcio <konradybcio@kernel.org>
Co-developed-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0af2f6be
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+20 −0
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@@ -14,6 +14,7 @@ description: |
  domains on Qualcomm SoCs.

  See also::
    include/dt-bindings/clock/qcom,sm6350-videocc.h
    include/dt-bindings/clock/qcom,videocc-sc7180.h
    include/dt-bindings/clock/qcom,videocc-sc7280.h
    include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -26,6 +27,7 @@ properties:
      - qcom,sc7180-videocc
      - qcom,sc7280-videocc
      - qcom,sdm845-videocc
      - qcom,sm6350-videocc
      - qcom,sm8150-videocc
      - qcom,sm8250-videocc

@@ -87,6 +89,24 @@ allOf:
            - const: bi_tcxo
            - const: bi_tcxo_ao

  - if:
      properties:
        compatible:
          enum:
            - qcom,sm6350-videocc
    then:
      properties:
        clocks:
          items:
            - description: Video AHB clock from GCC
            - description: Board XO source
            - description: Sleep Clock source
        clock-names:
          items:
            - const: iface
            - const: bi_tcxo
            - const: sleep_clk

  - if:
      properties:
        compatible:
+27 −0
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
 */

#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H

/* VIDEO_CC clocks */
#define VIDEO_PLL0			0
#define VIDEO_PLL0_OUT_EVEN             1
#define VIDEO_CC_IRIS_AHB_CLK		2
#define VIDEO_CC_IRIS_CLK_SRC		3
#define VIDEO_CC_MVS0_AXI_CLK		4
#define VIDEO_CC_MVS0_CORE_CLK		5
#define VIDEO_CC_MVSC_CORE_CLK		6
#define VIDEO_CC_MVSC_CTL_AXI_CLK	7
#define VIDEO_CC_SLEEP_CLK		8
#define VIDEO_CC_SLEEP_CLK_SRC		9
#define VIDEO_CC_VENUS_AHB_CLK		10

/* GDSCs */
#define MVSC_GDSC			0
#define MVS0_GDSC			1

#endif