Commit b8a98b6b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v5.16-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI fixes from Bjorn Helgaas:

 - Revert emulation of Marvell Armada A3720 expansion ROM because it
   doesn't work as expected (Marek Behún)

 - Assert PERST# in Apple M1 driver to fix initialization when booting
   from bootloaders using PCIe, such as U-Boot (Marc Zyngier)

 - Describe PERST# as active low in Apple T8103 DT and update driver to
   match (Marc Zyngier)

* tag 'pci-v5.16-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: apple: Fix PERST# polarity
  arm64: dts: apple: t8103: Mark PCIe PERST# polarity active low in DT
  PCI: apple: Follow the PCIe specifications when resetting the port
  Revert "PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge"
parents 2ca4b651 87620512

arch/arm64/boot/dts/apple/t8103.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 * Copyright The Asahi Linux Contributors

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/apple-aic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/pinctrl/apple.h>
@@ -281,7 +282,7 @@ pcie0: pcie@690000000 { 
			port00: pci@0,0 {

				device_type = "pci";

				reg = <0x0 0x0 0x0 0x0 0x0>;

				reset-gpios = <&pinctrl_ap 152 0>;

				reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;

				max-link-speed = <2>;



				#address-cells = <3>;
@@ -301,7 +302,7 @@ port00: pci@0,0 { 
			port01: pci@1,0 {

				device_type = "pci";

				reg = <0x800 0x0 0x0 0x0 0x0>;

				reset-gpios = <&pinctrl_ap 153 0>;

				reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;

				max-link-speed = <2>;



				#address-cells = <3>;
@@ -321,7 +322,7 @@ port01: pci@1,0 { 
			port02: pci@2,0 {

				device_type = "pci";

				reg = <0x1000 0x0 0x0 0x0 0x0>;

				reset-gpios = <&pinctrl_ap 33 0>;

				reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;

				max-link-speed = <1>;



				#address-cells = <3>;

drivers/pci/controller/pci-aardvark.c

+0 −9
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ 
#define PCIE_CORE_DEV_ID_REG					0x0

#define PCIE_CORE_CMD_STATUS_REG				0x4

#define PCIE_CORE_DEV_REV_REG					0x8

#define PCIE_CORE_EXP_ROM_BAR_REG				0x30

#define PCIE_CORE_PCIEXP_CAP					0xc0

#define PCIE_CORE_ERR_CAPCTL_REG				0x118

#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)
@@ -774,10 +773,6 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 
		*value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);

		return PCI_BRIDGE_EMUL_HANDLED;



	case PCI_ROM_ADDRESS1:

		*value = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);

		return PCI_BRIDGE_EMUL_HANDLED;



	case PCI_INTERRUPT_LINE: {

		/*

		 * From the whole 32bit register we support reading from HW only
@@ -810,10 +805,6 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 
		advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);

		break;



	case PCI_ROM_ADDRESS1:

		advk_writel(pcie, new, PCIE_CORE_EXP_ROM_BAR_REG);

		break;



	case PCI_INTERRUPT_LINE:

		if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {

			u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);

drivers/pci/controller/pcie-apple.c

+12 −2
Original line number Diff line number Diff line
@@ -516,7 +516,7 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie, 
	int ret, i;



	reset = gpiod_get_from_of_node(np, "reset-gpios", 0,

				       GPIOD_OUT_LOW, "#PERST");

				       GPIOD_OUT_LOW, "PERST#");

	if (IS_ERR(reset))

		return PTR_ERR(reset);
@@ -539,12 +539,22 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie, 


	rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);



	/* Assert PERST# before setting up the clock */

	gpiod_set_value(reset, 1);



	ret = apple_pcie_setup_refclk(pcie, port);

	if (ret < 0)

		return ret;



	/* The minimal Tperst-clk value is 100us (PCIe CEM r5.0, 2.9.2) */

	usleep_range(100, 200);



	/* Deassert PERST# */

	rmw_set(PORT_PERST_OFF, port->base + PORT_PERST);

	gpiod_set_value(reset, 1);

	gpiod_set_value(reset, 0);



	/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */

	msleep(100);



	ret = readl_relaxed_poll_timeout(port->base + PORT_STATUS, stat,

					 stat & PORT_STATUS_READY, 100, 250000);