Commit b8b56771 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Yury Norov (NVIDIA)
Browse files

clk: sp7021: switch to FIELD_PREP_WM16 macro 



The sp7021 clock driver has its own shifted high word mask macro,
similar to the ones many Rockchip drivers have.

Remove it, and replace instances of it with hw_bitfield.h's
FIELD_PREP_WM16 macro, which does the same thing except in a common
macro that also does compile-time error checking.

This was compile-tested with 32-bit ARM with Clang, no runtime tests
were performed as I lack the hardware. However, I verified that fix
commit 5c667d5a ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()")
is not regressed. No warning is produced.

Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarYury Norov (NVIDIA) <yury.norov@gmail.com>
parent 30e91957

drivers/clk/clk-sp7021.c

+8 −14
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/bitfield.h>

#include <linux/hw_bitfield.h>

#include <linux/slab.h>

#include <linux/io.h>

#include <linux/err.h>
@@ -38,13 +39,6 @@ enum { 
#define MASK_DIVN	GENMASK(7, 0)

#define MASK_DIVM	GENMASK(14, 8)



/* HIWORD_MASK FIELD_PREP */

#define HWM_FIELD_PREP(mask, value)		\

({						\

	u64 _m = mask;				\

	(_m << 16) | FIELD_PREP(_m, value);	\

})



struct sp_pll {

	struct clk_hw hw;

	void __iomem *reg;
@@ -313,15 +307,15 @@ static int plltv_set_rate(struct sp_pll *clk) 
	u32 r0, r1, r2;



	r0  = BIT(clk->bp_bit + 16);

	r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);

	r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);

	r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);

	r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);

	r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]);

	r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]);

	r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]);

	r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]);



	r1  = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);

	r1  = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]);



	r2  = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);

	r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);

	r2  = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1);

	r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1);



	spin_lock_irqsave(&clk->lock, flags);

	writel(r0, clk->reg);