Commit b8b6e6f1 authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher
Browse files

drm/amd: Add per-ring reset for vcn v4.0.0 use 

If there is a problem requiring a reset of the VCN engine, it is better to
reset the VCN engine rather than the entire GPU.

Add a reset callback for the ring which will stop and start VCN if an
issue happens.

Link: https://lore.kernel.org/r/20250506204948.12048-3-mario.limonciello@amd.com


Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d1a46cdd

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

+16 −1
Original line number Diff line number Diff line
@@ -239,9 +239,9 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 
			adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode;

	}



	/* TODO: Add queue reset mask when FW fully supports it */

	adev->vcn.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

	adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;



	if (amdgpu_sriov_vf(adev)) {

		r = amdgpu_virt_alloc_mm_table(adev);
@@ -1947,6 +1947,20 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 
	return 0;

}



static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];



	if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))

		return -EOPNOTSUPP;



	vcn_v4_0_stop(vinst);

	vcn_v4_0_start(vinst);



	return amdgpu_ring_test_helper(ring);

}



static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {

	.type = AMDGPU_RING_TYPE_VCN_ENC,

	.align_mask = 0x3f,
@@ -1976,6 +1990,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 
	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

	.reset = vcn_v4_0_ring_reset,

};



/**