Commit b8ef623f authored by Christian Bruel's avatar Christian Bruel Committed by Bjorn Helgaas
Browse files

dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings 



STM32MP25 PCIe Controller is based on the DesignWare core configured as
endpoint mode from the SYSCFG register.

Signed-off-by: default avatarChristian Bruel <christian.bruel@foss.st.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250820075411.1178729-6-christian.bruel@foss.st.com
parent 63a562b3

Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STMicroelectronics STM32MP25 PCIe Endpoint



maintainers:

  - Christian Bruel <christian.bruel@foss.st.com>



description:

  PCIe endpoint controller based on the Synopsys DesignWare PCIe core.



allOf:

  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#



properties:

  compatible:

    const: st,stm32mp25-pcie-ep



  reg:

    items:

      - description: Data Bus Interface (DBI) registers.

      - description: Data Bus Interface (DBI) shadow registers.

      - description: Internal Address Translation Unit (iATU) registers.

      - description: PCIe configuration registers.



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: addr_space



  reset-gpios:

    description: GPIO controlled connection to PERST# signal

    maxItems: 1



  phys:

    maxItems: 1



required:

  - phys

  - reset-gpios



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/st,stm32mp25-rcc.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/reset/st,stm32mp25-rcc.h>



    pcie-ep@48400000 {

        compatible = "st,stm32mp25-pcie-ep";

        reg = <0x48400000 0x400000>,

              <0x48500000 0x100000>,

              <0x48700000 0x80000>,

              <0x10000000 0x10000000>;

        reg-names = "dbi", "dbi2", "atu", "addr_space";

        clocks = <&rcc CK_BUS_PCIE>;

        phys = <&combophy PHY_TYPE_PCIE>;

        resets = <&rcc PCIE_R>;

        pinctrl-names = "default", "init";

        pinctrl-0 = <&pcie_pins_a>;

        pinctrl-1 = <&pcie_init_pins_a>;

        reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;

        access-controllers = <&rifsc 68>;

        power-domains = <&CLUSTER_PD>;

    };