Commit b8f669b4 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Honor trap routing for FPMR 



HCRX_EL2.EnFPM controls the trapping of FPMR (as well as the validity
of any FP8 instruction, but we don't really care about this last part).

Describe the trap bit so that the exception can be reinjected in a
NV guest.

Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Tested-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-6-maz@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent ef3be860

arch/arm64/kvm/emulate-nested.c

+8 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ enum cgt_group_id { 
	CGT_CPTR_TAM,

	CGT_CPTR_TCPAC,



	CGT_HCRX_EnFPM,

	CGT_HCRX_TCR2En,



	/*
@@ -372,6 +373,12 @@ static const struct trap_bits coarse_trap_bits[] = { 
		.mask		= CPTR_EL2_TCPAC,

		.behaviour	= BEHAVE_FORWARD_ANY,

	},

	[CGT_HCRX_EnFPM] = {

		.index		= HCRX_EL2,

		.value 		= 0,

		.mask		= HCRX_EL2_EnFPM,

		.behaviour	= BEHAVE_FORWARD_ANY,

	},

	[CGT_HCRX_TCR2En] = {

		.index		= HCRX_EL2,

		.value 		= 0,
@@ -1108,6 +1115,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 
	SR_TRAP(SYS_CNTP_CTL_EL0,	CGT_CNTHCTL_EL1PTEN),

	SR_TRAP(SYS_CNTPCT_EL0,		CGT_CNTHCTL_EL1PCTEN),

	SR_TRAP(SYS_CNTPCTSS_EL0,	CGT_CNTHCTL_EL1PCTEN),

	SR_TRAP(SYS_FPMR,		CGT_HCRX_EnFPM),

};



static DEFINE_XARRAY(sr_forward_xa);