Commit b914ec33 authored by Frank Oltmanns's avatar Frank Oltmanns Committed by Jernej Skrabec
Browse files

clk: sunxi-ng: common: Support minimum and maximum rate 



The Allwinner SoC's typically have an upper and lower limit for their
clocks' rates. Up until now, support for that has been implemented
separately for each clock type.

Implement that functionality in the sunxi-ng's common part making use of
the CCF rate liming capabilities, so that it is available for all clock
types.

Suggested-by: default avatarMaxime Ripard <mripard@kernel.org>
Signed-off-by: default avatarFrank Oltmanns <frank@oltmanns.dev>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-1-46fc80c83637@oltmanns.dev


Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent 7e91ed76

drivers/clk/sunxi-ng/ccu_common.c

+19 −0
Original line number Diff line number Diff line
@@ -44,6 +44,16 @@ bool ccu_is_better_rate(struct ccu_common *common, 
			unsigned long current_rate,

			unsigned long best_rate)

{

	unsigned long min_rate, max_rate;



	clk_hw_get_rate_range(&common->hw, &min_rate, &max_rate);



	if (current_rate > max_rate)

		return false;



	if (current_rate < min_rate)

		return false;



	if (common->features & CCU_FEATURE_CLOSEST_RATE)

		return abs(current_rate - target_rate) < abs(best_rate - target_rate);
@@ -122,6 +132,7 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, 


	for (i = 0; i < desc->hw_clks->num ; i++) {

		struct clk_hw *hw = desc->hw_clks->hws[i];

		struct ccu_common *common = hw_to_ccu_common(hw);

		const char *name;



		if (!hw)
@@ -136,6 +147,14 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, 
			pr_err("Couldn't register clock %d - %s\n", i, name);

			goto err_clk_unreg;

		}



		if (common->max_rate)

			clk_hw_set_rate_range(hw, common->min_rate,

					      common->max_rate);

		else

			WARN(common->min_rate,

			     "No max_rate, ignoring min_rate of clock %d - %s\n",

			     i, name);

	}



	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,

drivers/clk/sunxi-ng/ccu_common.h

+3 −0
Original line number Diff line number Diff line
@@ -31,6 +31,9 @@ struct ccu_common { 
	u16		lock_reg;

	u32		prediv;



	unsigned long	min_rate;

	unsigned long	max_rate;



	unsigned long	features;

	spinlock_t	*lock;

	struct clk_hw	hw;