Commit b9802de9 authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Gustavo Sousa
Browse files

drm/i915/xe3p_lpd: Drop support for interlace mode 



Interlace mode is officially removed from HW from Xe3p_LPD.  The
register TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so
make sure we do not set/get these anymore.

Bspec: 69961, 70000
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-10-00e87b510ae7@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
parent b8118807

drivers/gpu/drm/i915/display/intel_display.c

+8 −6
Original line number Diff line number Diff line
@@ -2657,7 +2657,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta 
		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;

	}



	if (DISPLAY_VER(display) >= 4)

	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)

		intel_de_write(display,

			       TRANS_VSYNCSHIFT(display, cpu_transcoder),

			       vsyncshift);
@@ -2798,7 +2798,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 
	struct intel_display *display = to_intel_display(crtc_state);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;



	if (DISPLAY_VER(display) == 2)

	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)

		return false;



	if (DISPLAY_VER(display) >= 9 ||
@@ -3189,10 +3189,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 
	if (display->platform.haswell && crtc_state->dither)

		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;



	if (DISPLAY_VER(display) < 35) {

		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

			val |= TRANSCONF_INTERLACE_IF_ID_ILK;

		else

			val |= TRANSCONF_INTERLACE_PF_PD_ILK;

	}



	if (display->platform.haswell &&

	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)