Commit b993744a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'loongarch-fixes-6.19-1' of... 

Merge tag 'loongarch-fixes-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch fixes from Huacai Chen:
 "Complete CPUCFG registers definition, set correct protection_map[] for
  VM_NONE/VM_SHARED, fix some bugs in the orc stack unwinder, ftrace and
  BPF JIT"

* tag 'loongarch-fixes-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  samples/ftrace: Adjust LoongArch register restore order in direct calls
  LoongArch: BPF: Enhance the bpf_arch_text_poke() function
  LoongArch: BPF: Enable trampoline-based tracing for module functions
  LoongArch: BPF: Adjust the jump offset of tail calls
  LoongArch: BPF: Save return address register ra to t0 before trampoline
  LoongArch: BPF: Zero-extend bpf_tail_call() index
  LoongArch: BPF: Sign extend kfunc call arguments
  LoongArch: Refactor register restoration in ftrace_common_return
  LoongArch: Enable exception fixup for specific ADE subcode
  LoongArch: Remove unnecessary checks for ORC unwinder
  LoongArch: Remove is_entry_func() and kernel_entry_end
  LoongArch: Use UNWIND_HINT_END_OF_STACK for entry points
  LoongArch: Set correct protection_map[] for VM_NONE/VM_SHARED
  LoongArch: Complete CPUCFG registers definition
parents 9b043680 bb85d206

arch/loongarch/include/asm/loongarch.h

+7 −0
Original line number Diff line number Diff line
@@ -94,6 +94,12 @@ 
#define  CPUCFG2_LSPW			BIT(21)

#define  CPUCFG2_LAM			BIT(22)

#define  CPUCFG2_PTW			BIT(24)

#define  CPUCFG2_FRECIPE		BIT(25)

#define  CPUCFG2_DIV32			BIT(26)

#define  CPUCFG2_LAM_BH			BIT(27)

#define  CPUCFG2_LAMCAS			BIT(28)

#define  CPUCFG2_LLACQ_SCREL		BIT(29)

#define  CPUCFG2_SCQ			BIT(30)



#define LOONGARCH_CPUCFG3		0x3

#define  CPUCFG3_CCDMA			BIT(0)
@@ -108,6 +114,7 @@ 
#define  CPUCFG3_SPW_HG_HF		BIT(11)

#define  CPUCFG3_RVA			BIT(12)

#define  CPUCFG3_RVAMAX			GENMASK(16, 13)

#define  CPUCFG3_DBAR_HINTS		BIT(17)

#define  CPUCFG3_ALDORDER_CAP		BIT(18) /* All address load ordered, capability */

#define  CPUCFG3_ASTORDER_CAP		BIT(19) /* All address store ordered, capability */

#define  CPUCFG3_ALDORDER_STA		BIT(20) /* All address load ordered, status */

arch/loongarch/kernel/head.S

+2 −2
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ SYM_DATA(kernel_fsize, .long _kernel_fsize); 
	.align 12



SYM_CODE_START(kernel_entry)			# kernel entry point

	UNWIND_HINT_END_OF_STACK



	SETUP_TWINS

	SETUP_MODES	t0
@@ -113,6 +114,7 @@ SYM_CODE_END(kernel_entry) 
 * function after setting up the stack and tp registers.

 */

SYM_CODE_START(smpboot_entry)

	UNWIND_HINT_END_OF_STACK



	SETUP_TWINS

	SETUP_MODES	t0
@@ -142,5 +144,3 @@ SYM_CODE_START(smpboot_entry) 
SYM_CODE_END(smpboot_entry)



#endif /* CONFIG_SMP */
 


SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)

arch/loongarch/kernel/mcount_dyn.S

+10 −4
Original line number Diff line number Diff line
@@ -94,7 +94,6 @@ SYM_INNER_LABEL(ftrace_graph_call, SYM_L_GLOBAL) 
 * at the callsite, so there is no need to restore the T series regs.

 */

ftrace_common_return:

	PTR_L		ra, sp, PT_R1

	PTR_L		a0, sp, PT_R4

	PTR_L		a1, sp, PT_R5

	PTR_L		a2, sp, PT_R6
@@ -104,12 +103,17 @@ ftrace_common_return: 
	PTR_L		a6, sp, PT_R10

	PTR_L		a7, sp, PT_R11

	PTR_L		fp, sp, PT_R22

	PTR_L		t0, sp, PT_ERA

	PTR_L		t1, sp, PT_R13

	PTR_ADDI	sp, sp, PT_SIZE

	bnez		t1, .Ldirect



	PTR_L		ra, sp, PT_R1

	PTR_L		t0, sp, PT_ERA

	PTR_ADDI	sp, sp, PT_SIZE

	jr		t0

.Ldirect:

	PTR_L		t0, sp, PT_R1

	PTR_L		ra, sp, PT_ERA

	PTR_ADDI	sp, sp, PT_SIZE

	jr		t1

SYM_CODE_END(ftrace_common)
@@ -161,6 +165,8 @@ SYM_CODE_END(return_to_handler) 
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS

SYM_CODE_START(ftrace_stub_direct_tramp)

	UNWIND_HINT_UNDEFINED

	jr		t0

	move		t1, ra

	move		ra, t0

	jr		t1

SYM_CODE_END(ftrace_stub_direct_tramp)

#endif /* CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS */

arch/loongarch/kernel/traps.c

+5 −0
Original line number Diff line number Diff line
@@ -535,10 +535,15 @@ asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 
asmlinkage void noinstr do_ade(struct pt_regs *regs)

{

	irqentry_state_t state = irqentry_enter(regs);

	unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, regs->csr_estat);



	if ((esubcode == EXSUBCODE_ADEM) && fixup_exception(regs))

		goto out;



	die_if_kernel("Kernel ade access", regs);

	force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);



out:

	irqentry_exit(regs, state);

}

arch/loongarch/kernel/unwind_orc.c

+5 −22
Original line number Diff line number Diff line
@@ -348,24 +348,10 @@ void unwind_start(struct unwind_state *state, struct task_struct *task, 
}

EXPORT_SYMBOL_GPL(unwind_start);



static bool is_entry_func(unsigned long addr)

{

	extern u32 kernel_entry;

	extern u32 kernel_entry_end;



	return addr >= (unsigned long)&kernel_entry && addr < (unsigned long)&kernel_entry_end;

}



static inline unsigned long bt_address(unsigned long ra)

{

	extern unsigned long eentry;



	if (__kernel_text_address(ra))

		return ra;



	if (__module_text_address(ra))

		return ra;



	if (ra >= eentry && ra < eentry +  EXCCODE_INT_END * VECSIZE) {

		unsigned long func;

		unsigned long type = (ra - eentry) / VECSIZE;
@@ -383,10 +369,13 @@ static inline unsigned long bt_address(unsigned long ra) 
			break;

		}



		return func + offset;

		ra = func + offset;

	}



	if (__kernel_text_address(ra))

		return ra;



	return 0;

}



bool unwind_next_frame(struct unwind_state *state)
@@ -402,9 +391,6 @@ bool unwind_next_frame(struct unwind_state *state) 
	/* Don't let modules unload while we're reading their ORC data. */

	guard(rcu)();



	if (is_entry_func(state->pc))

		goto end;



	orc = orc_find(state->pc);

	if (!orc) {

		/*
@@ -512,9 +498,6 @@ bool unwind_next_frame(struct unwind_state *state) 
		goto err;

	}



	if (!__kernel_text_address(state->pc))

		goto err;



	return true;



err: