Commit b99dcb91 authored by Raag Jadav's avatar Raag Jadav Committed by Andi Shyti
Browse files

drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges 



Refactor DG2 PCI IDs into D, E and M ranges which will be useful for
segment specific features.

v3: Rework subplatform naming (Jani)

Signed-off-by: default avatarRaag Jadav <raag.jadav@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRiana Tauro <riana.tauro@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-2-raag.jadav@intel.com
parent e7f0a3a6

include/drm/intel/pciids.h

+42 −13
Original line number Diff line number Diff line
@@ -717,37 +717,66 @@ 
	MACRO__(0xA7AB, ## __VA_ARGS__)



/* DG2 */

#define INTEL_DG2_G10_IDS(MACRO__, ...) \

	MACRO__(0x5690, ## __VA_ARGS__), \

	MACRO__(0x5691, ## __VA_ARGS__), \

	MACRO__(0x5692, ## __VA_ARGS__), \

#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \

	MACRO__(0x56A0, ## __VA_ARGS__), \

	MACRO__(0x56A1, ## __VA_ARGS__), \

	MACRO__(0x56A2, ## __VA_ARGS__), \

	MACRO__(0x56A2, ## __VA_ARGS__)



#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \

	MACRO__(0x56BE, ## __VA_ARGS__), \

	MACRO__(0x56BF, ## __VA_ARGS__)



#define INTEL_DG2_G11_IDS(MACRO__, ...) \

	MACRO__(0x5693, ## __VA_ARGS__), \

	MACRO__(0x5694, ## __VA_ARGS__), \

	MACRO__(0x5695, ## __VA_ARGS__), \

#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \

	MACRO__(0x5690, ## __VA_ARGS__), \

	MACRO__(0x5691, ## __VA_ARGS__), \

	MACRO__(0x5692, ## __VA_ARGS__)



#define INTEL_DG2_G10_IDS(MACRO__, ...) \

	INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)



#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \

	MACRO__(0x56A5, ## __VA_ARGS__), \

	MACRO__(0x56A6, ## __VA_ARGS__), \

	MACRO__(0x56B0, ## __VA_ARGS__), \

	MACRO__(0x56B1, ## __VA_ARGS__), \

	MACRO__(0x56B1, ## __VA_ARGS__)



#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \

	MACRO__(0x56BA, ## __VA_ARGS__), \

	MACRO__(0x56BB, ## __VA_ARGS__), \

	MACRO__(0x56BC, ## __VA_ARGS__), \

	MACRO__(0x56BD, ## __VA_ARGS__)



#define INTEL_DG2_G12_IDS(MACRO__, ...) \

	MACRO__(0x5696, ## __VA_ARGS__), \

	MACRO__(0x5697, ## __VA_ARGS__), \

#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \

	MACRO__(0x5693, ## __VA_ARGS__), \

	MACRO__(0x5694, ## __VA_ARGS__), \

	MACRO__(0x5695, ## __VA_ARGS__)



#define INTEL_DG2_G11_IDS(MACRO__, ...) \

	INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)



#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \

	MACRO__(0x56A3, ## __VA_ARGS__), \

	MACRO__(0x56A4, ## __VA_ARGS__), \

	MACRO__(0x56B2, ## __VA_ARGS__), \

	MACRO__(0x56B3, ## __VA_ARGS__)



#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \

	MACRO__(0x5696, ## __VA_ARGS__), \

	MACRO__(0x5697, ## __VA_ARGS__)



#define INTEL_DG2_G12_IDS(MACRO__, ...) \

	INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)



#define INTEL_DG2_D_IDS(MACRO__, ...) \

	INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)



#define INTEL_DG2_IDS(MACRO__, ...) \

	INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \

	INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \