Loading arch/arm/boot/dts/omap5.dtsi +11 −8 Original line number Diff line number Diff line Loading @@ -18,6 +18,9 @@ /include/ "skeleton.dtsi" / { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap5"; interrupt-parent = <&gic>; Loading Loading @@ -47,6 +50,14 @@ timer { clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>; }; /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. Loading Loading @@ -96,14 +107,6 @@ omap5_pmx_wkup: pinmux@4ae0c840 { pinctrl-single,function-mask = <0x7fff>; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>; }; sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; Loading Loading
arch/arm/boot/dts/omap5.dtsi +11 −8 Original line number Diff line number Diff line Loading @@ -18,6 +18,9 @@ /include/ "skeleton.dtsi" / { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap5"; interrupt-parent = <&gic>; Loading Loading @@ -47,6 +50,14 @@ timer { clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>; }; /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. Loading Loading @@ -96,14 +107,6 @@ omap5_pmx_wkup: pinmux@4ae0c840 { pinctrl-single,function-mask = <0x7fff>; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>; }; sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; Loading