Commit ba1aefee authored by Shruti Parab's avatar Shruti Parab Committed by Paolo Abeni
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bnxt_en: Add fw log trace support for 5731X/5741X chips



These older chips now support the fw log traces via backing store
qcaps_v2. No other backing store memory types are supported besides
the fw trace types.

Reviewed-by: default avatarHongguang Gao <hongguang.gao@broadcom.com>
Reviewed-by: default avatarAndy Gospodarek <andrew.gospodarek@broadcom.com>
Signed-off-by: default avatarShruti Parab <shruti.parab@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Link: https://patch.msgid.link/20250917040839.1924698-6-michael.chan@broadcom.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent de676875
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+7 −2
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ const u16 bnxt_bstore_to_trace[] = {
	[BNXT_CTX_CA1]		= DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE,
	[BNXT_CTX_CA2]		= DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE,
	[BNXT_CTX_RIGP1]	= DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE,
	[BNXT_CTX_KONG]		= DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE,
};

static struct workqueue_struct *bnxt_pf_wq;
@@ -9158,7 +9159,7 @@ static int bnxt_backing_store_cfg_v2(struct bnxt *bp)
	int rc = 0;
	u16 type;

	for (type = BNXT_CTX_SRT; type <= BNXT_CTX_RIGP1; type++) {
	for (type = BNXT_CTX_SRT; type <= BNXT_CTX_KONG; type++) {
		ctxm = &ctx->ctx_arr[type];
		if (!bnxt_bs_trace_avail(bp, type))
			continue;
@@ -9309,6 +9310,10 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
	if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
		return 0;

	ena = 0;
	if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
		goto skip_legacy;

	ctxm = &ctx->ctx_arr[BNXT_CTX_QP];
	l2_qps = ctxm->qp_l2_entries;
	qp1_qps = ctxm->qp_qp1_entries;
@@ -9317,7 +9322,6 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
	ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ];
	srqs = ctxm->srq_l2_entries;
	max_srqs = ctxm->max_entries;
	ena = 0;
	if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
		pg_lvl = 2;
		if (BNXT_SW_RES_LMT(bp)) {
@@ -9411,6 +9415,7 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
		ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
	ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;

skip_legacy:
	if (bp->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2)
		rc = bnxt_backing_store_cfg_v2(bp);
	else
+2 −1
Original line number Diff line number Diff line
@@ -1968,10 +1968,11 @@ struct bnxt_ctx_mem_type {
#define BNXT_CTX_CA1	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE
#define BNXT_CTX_CA2	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE
#define BNXT_CTX_RIGP1	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE
#define BNXT_CTX_KONG	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE

#define BNXT_CTX_MAX	(BNXT_CTX_TIM + 1)
#define BNXT_CTX_L2_MAX	(BNXT_CTX_FTQM + 1)
#define BNXT_CTX_V2_MAX	(BNXT_CTX_RIGP1 + 1)
#define BNXT_CTX_V2_MAX	(BNXT_CTX_KONG + 1)
#define BNXT_CTX_INV	((u16)-1)

struct bnxt_ctx_mem_info {
+2 −1
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ static const u16 bnxt_bstore_to_seg_id[] = {
	[BNXT_CTX_CA1]			= BNXT_CTX_MEM_SEG_CA1,
	[BNXT_CTX_CA2]			= BNXT_CTX_MEM_SEG_CA2,
	[BNXT_CTX_RIGP1]		= BNXT_CTX_MEM_SEG_RIGP1,
	[BNXT_CTX_KONG]			= BNXT_CTX_MEM_SEG_KONG,
};

static int bnxt_dbg_hwrm_log_buffer_flush(struct bnxt *bp, u16 type, u32 flags,
@@ -359,7 +360,7 @@ static u32 bnxt_get_ctx_coredump(struct bnxt *bp, void *buf, u32 offset,

	if (buf)
		buf += offset;
	for (type = 0 ; type <= BNXT_CTX_RIGP1; type++) {
	for (type = 0; type <= BNXT_CTX_KONG; type++) {
		struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type];
		bool trace = bnxt_bs_trace_avail(bp, type);
		u32 seg_id = bnxt_bstore_to_seg_id[type];
+1 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ struct bnxt_driver_segment_record {
#define BNXT_CTX_MEM_SEG_CA1	0x9
#define BNXT_CTX_MEM_SEG_CA2	0xa
#define BNXT_CTX_MEM_SEG_RIGP1	0xb
#define BNXT_CTX_MEM_SEG_KONG	0xd

#define BNXT_CRASH_DUMP_LEN	(8 << 20)