Commit ba1ec92c authored by Cosmin Tanislav's avatar Cosmin Tanislav Committed by Geert Uytterhoeven
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clk: renesas: r9a09g077: Add ADC module clocks 



Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12-bit
ADC peripherals, each with their own peripheral clock.

For conversion, they use the PCLKL clock.

Add their clocks to the list of module clocks.

Signed-off-by: default avatarCosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250923160524.1096720-2-cosmin-gabriel.tanislav.xa@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b91401af

drivers/clk/renesas/r9a09g077-cpg.c

+3 −0
Original line number Diff line number Diff line
@@ -188,6 +188,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { 
	DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),

	DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),

	DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),

	DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),

	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),

	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),

	DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),