Commit ba51cf9f authored by Michael Guralnik's avatar Michael Guralnik Committed by Leon Romanovsky
Browse files

net/mlx5: Drop MR cache related code 



Following mlx5_ib move to using FRMR pools, drop all unused code of MR
cache.

Signed-off-by: default avatarMichael Guralnik <michaelgur@nvidia.com>
Reviewed-by: default avatarYishai Hadas <yishaih@nvidia.com>
Signed-off-by: default avatarEdward Srouji <edwards@nvidia.com>
Link: https://patch.msgid.link/20260226-frmr_pools-v4-7-95360b54f15e@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 36680ef7

drivers/net/ethernet/mellanox/mlx5/core/main.c

+1 −66
Original line number Diff line number Diff line
@@ -110,74 +110,9 @@ static struct mlx5_profile profile[] = { 


	},

	[2] = {

		.mask		= MLX5_PROF_MASK_QP_SIZE |

				  MLX5_PROF_MASK_MR_CACHE,

		.mask		= MLX5_PROF_MASK_QP_SIZE,

		.log_max_qp	= LOG_MAX_SUPPORTED_QPS,

		.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,

		.mr_cache[0]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[1]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[2]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[3]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[4]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[5]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[6]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[7]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[8]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[9]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[10]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[11]	= {

			.size	= 500,

			.limit	= 250

		},

		.mr_cache[12]	= {

			.size	= 64,

			.limit	= 32

		},

		.mr_cache[13]	= {

			.size	= 32,

			.limit	= 16

		},

		.mr_cache[14]	= {

			.size	= 16,

			.limit	= 8

		},

		.mr_cache[15]	= {

			.size	= 8,

			.limit	= 4

		},

	},

	[3] = {

		.mask		= MLX5_PROF_MASK_QP_SIZE,

include/linux/mlx5/driver.h

+0 −11
Original line number Diff line number Diff line
@@ -705,23 +705,12 @@ struct mlx5_st; 


enum {

	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,

	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,

};



enum {

	MKEY_CACHE_LAST_STD_ENTRY = 20,

	MLX5_IMR_KSM_CACHE_ENTRY,

	MAX_MKEY_CACHE_ENTRIES

};



struct mlx5_profile {

	u64	mask;

	u8	log_max_qp;

	u8	num_cmd_caches;

	struct {

		int	size;

		int	limit;

	} mr_cache[MAX_MKEY_CACHE_ENTRIES];

};



struct mlx5_hca_cap {