Commit ba531117 authored by Yunxiang Li's avatar Yunxiang Li Committed by Alex Deucher
Browse files

drm/amdgpu: call flush_gpu_tlb directly in gfxhub enable



Here since we are in reset and takes the reset_domain write side lock
already. We can't use the flush tlb helper which tries to take the read
side.

Signed-off-by: default avatarYunxiang Li <Yunxiang.Li@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1f9d82b
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+1 −3
Original line number Diff line number Diff line
@@ -620,10 +620,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
	int r;

	if (!hub->sdma_invalidation_workaround || vmid ||
	    !adev->mman.buffer_funcs_enabled ||
	    !adev->ib_pool_ready || amdgpu_in_reset(adev) ||
	    !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||
	    !ring->sched.ready) {

		/*
		 * A GPU reset should flush all TLBs anyway, so no need to do
		 * this while one is ongoing.
+3 −1
Original line number Diff line number Diff line
@@ -4415,7 +4415,9 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
		false : true;

	adev->gfxhub.funcs->set_fault_enable_default(adev, value);
	amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
	/* TODO investigate why this and the hdp flush above is needed,
	 * are we missing a flush somewhere else? */
	adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);

	return 0;
}
+3 −1
Original line number Diff line number Diff line
@@ -3192,7 +3192,9 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
		false : true;

	adev->gfxhub.funcs->set_fault_enable_default(adev, value);
	amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
	/* TODO investigate why this and the hdp flush above is needed,
	 * are we missing a flush somewhere else? */
	adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);

	return 0;
}