Commit ba6ec099 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 



Cross-merge networking fixes after downstream PR (net-6.14-rc2).

No conflicts or adjacent changes.

Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 0bdcfaf8 3cf0a98f

.mailmap

+8 −1
Original line number Diff line number Diff line
@@ -142,13 +142,17 @@ Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> 
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>

Brendan Higgins <brendan.higgins@linux.dev> <brendanhiggins@google.com>

Brian Avery <b.avery@hp.com>

Brian Cain <bcain@kernel.org> <brian.cain@oss.qualcomm.com>

Brian Cain <bcain@kernel.org> <bcain@quicinc.com>

Brian King <brking@us.ibm.com>

Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com>

Bryan Tan <bryan-bt.tan@broadcom.com> <bryantan@vmware.com>

Cai Huoqing <cai.huoqing@linux.dev> <caihuoqing@baidu.com>

Can Guo <quic_cang@quicinc.com> <cang@codeaurora.org>

Carl Huang <quic_cjhuang@quicinc.com> <cjhuang@codeaurora.org>

Carlos Bilbao <carlos.bilbao.osdev@gmail.com> <carlos.bilbao@amd.com>

Carlos Bilbao <carlos.bilbao@kernel.org> <carlos.bilbao@amd.com>

Carlos Bilbao <carlos.bilbao@kernel.org> <carlos.bilbao.osdev@gmail.com>

Carlos Bilbao <carlos.bilbao@kernel.org> <bilbao@vt.edu>

Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>

Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>

Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>
@@ -165,6 +169,7 @@ Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com> 
Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>

Christian Marangi <ansuelsmth@gmail.com>

Christophe Ricard <christophe.ricard@gmail.com>

Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>

Christoph Hellwig <hch@lst.de>

Chuck Lever <chuck.lever@oracle.com> <cel@kernel.org>

Chuck Lever <chuck.lever@oracle.com> <cel@netapp.com>
@@ -261,6 +266,7 @@ Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com> 
Guru Das Srinagesh <quic_gurus@quicinc.com> <gurus@codeaurora.org>

Gustavo Padovan <gustavo@las.ic.unicamp.br>

Gustavo Padovan <padovan@profusion.mobi>

Hamza Mahfooz <hamzamahfooz@linux.microsoft.com> <hamza.mahfooz@amd.com>

Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>

Hans Verkuil <hverkuil@xs4all.nl> <hansverk@cisco.com>

Hans Verkuil <hverkuil@xs4all.nl> <hverkuil-cisco@xs4all.nl>
@@ -761,6 +767,7 @@ Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de> 
Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>

Yanteng Si <si.yanteng@linux.dev> <siyanteng@loongson.cn>

Ying Huang <huang.ying.caritas@gmail.com> <ying.huang@intel.com>

Yosry Ahmed <yosry.ahmed@linux.dev> <yosryahmed@google.com>

Yusuke Goda <goda.yusuke@renesas.com>

Zack Rusin <zack.rusin@broadcom.com> <zackr@vmware.com>

Zhu Yanjun <zyjzyj2000@gmail.com> <yanjunz@nvidia.com>

Documentation/arch/riscv/hwprobe.rst

+10 −0
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@@ -293,3 +293,13 @@ The following keys are defined: 


  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are

    not supported at all and will generate a misaligned address fault.



* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the

  thead vendor extensions that are compatible with the

  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.



  * T-HEAD



    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor

        extension is supported in the T-Head ISA extensions spec starting from

	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").

Documentation/devicetree/bindings/arm/fsl.yaml

+3 −0
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@@ -1091,6 +1091,7 @@ properties: 
              - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC

              - emcraft,imx8mp-navqp      # i.MX8MP Emcraft Systems NavQ+ Kit

              - fsl,imx8mp-evk            # i.MX8MP EVK Board

              - fsl,imx8mp-evk-revb4      # i.MX8MP EVK Rev B4 Board

              - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board

              - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board

              - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
@@ -1271,6 +1272,7 @@ properties: 
        items:

          - enum:

              - fsl,imx8qm-mek           # i.MX8QM MEK Board

              - fsl,imx8qm-mek-revd      # i.MX8QM MEK Rev D Board

              - toradex,apalis-imx8      # Apalis iMX8 Modules

              - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules

          - const: fsl,imx8qm
@@ -1299,6 +1301,7 @@ properties: 
          - enum:

              - einfochips,imx8qxp-ai_ml  # i.MX8QXP AI_ML Board

              - fsl,imx8qxp-mek           # i.MX8QXP MEK Board

              - fsl,imx8qxp-mek-wcpu      # i.MX8QXP MEK WCPU Board

          - const: fsl,imx8qxp



      - description: i.MX8DXL based Boards

Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml

+2 −3
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@@ -14,9 +14,8 @@ allOf: 


description: |

  The Microchip LAN966x outband interrupt controller (OIC) maps the internal

  interrupt sources of the LAN966x device to an external interrupt.

  When the LAN966x device is used as a PCI device, the external interrupt is

  routed to the PCI interrupt.

  interrupt sources of the LAN966x device to a PCI interrupt when the LAN966x

  device is used as a PCI device.



properties:

  compatible:

Documentation/devicetree/bindings/riscv/cpus.yaml

+19 −0
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@@ -26,6 +26,18 @@ description: | 
allOf:

  - $ref: /schemas/cpu.yaml#

  - $ref: extensions.yaml

  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - thead,c906

                - thead,c910

                - thead,c920

    then:

      properties:

        thead,vlenb: false



properties:

  compatible:
@@ -96,6 +108,13 @@ properties: 
    description:

      The blocksize in bytes for the Zicboz cache operations.



  thead,vlenb:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      VLEN/8, the vector register length in bytes. This property is required on

      thead systems where the vector register length is not identical on all harts, or

      the vlenb CSR is not available.



  # RISC-V has multiple properties for cache op block sizes as the sizes

  # differ between individual CBO extensions

  cache-op-block-size: false