Commit ba73d69a authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Force max clocks unconditionally when p-state is unsupported 



[WHY&HOW]
UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update
to SMU.  When this happens, the UCLK provided should be max if switching is
unsupported.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 028383b6

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

+20 −16
Original line number Diff line number Diff line
@@ -791,13 +791,15 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( 
				block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;

				num_steps++;

			}

		} else {

			/* P-State is not supported so force max clocks */

		}

	}



	if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {

		/* when P-State switching disabled, set UCLK min = max */

		idle_fclk_mhz =

				clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;

		active_fclk_mhz = idle_fclk_mhz;

	}

	}



	/* UPDATE DCFCLK */

	if (dc->debug.force_min_dcfclk_mhz > 0)
@@ -872,8 +874,11 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( 
				block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;

				num_steps++;

			}

		} else {

			/* when disabling P-State switching, set UCLK min = max */

		}

	}



	if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

		/* when P-State switching disabled, set UCLK min = max */

		if (dc->clk_mgr->dc_mode_softmax_enabled) {

			/* will never have the functional UCLK min above the softmax

			* since we calculate mode support based on softmax being the max UCLK
@@ -885,7 +890,6 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( 
		}

		idle_uclk_mhz = active_uclk_mhz;

	}

	}



	/* Always update saved value, even if new value not set due to P-State switching unsupported */

	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {