Commit ba7a94ea authored by Jonathan Marek's avatar Jonathan Marek Committed by Abhinav Kumar
Browse files

drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes 



Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.

Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Patchwork: https://patchwork.freedesktop.org/patch/545548/
Link: https://lore.kernel.org/r/20230704160106.26055-1-jonathan@marek.ca


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent a85c238c

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+7 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 


static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,

	CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,

	1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};

	1, 2, 3, 4, 5};



static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,

		enum dpu_lm lm)
@@ -198,6 +198,12 @@ static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx, 
	case SSPP_DMA3:

		ctx->pending_flush_mask |= BIT(25);

		break;

	case SSPP_DMA4:

		ctx->pending_flush_mask |= BIT(13);

		break;

	case SSPP_DMA5:

		ctx->pending_flush_mask |= BIT(14);

		break;

	case SSPP_CURSOR0:

		ctx->pending_flush_mask |= BIT(22);

		break;