Commit bb4ed26e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull RISC-V SoC updates from Arnd Bergmann:
 "Add support for StarFive JH7100 RISC-V SoC

  This adds support for the StarFive JH7100, including the necessary
  device drivers and DT files for the BeagleV Starlight prototype board,
  with additional boards to be added later. This SoC promises to be the
  first usable low-cost platform for RISC-V.

  I've taken this through the SoC tree in the anticipation of adding a
  few other Arm based SoCs as well, but those did not pass the review in
  time, so it's only this one"

* tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  reset: starfive-jh7100: Fix 32bit compilation
  RISC-V: Add BeagleV Starlight Beta device tree
  RISC-V: Add initial StarFive JH7100 device tree
  serial: 8250_dw: Add StarFive JH7100 quirk
  dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
  pinctrl: starfive: Add pinctrl driver for StarFive SoCs
  dt-bindings: pinctrl: Add StarFive JH7100 bindings
  dt-bindings: pinctrl: Add StarFive pinctrl definitions
  reset: starfive-jh7100: Add StarFive JH7100 reset driver
  dt-bindings: reset: Add Starfive JH7100 reset bindings
  dt-bindings: reset: Add StarFive JH7100 reset definitions
  clk: starfive: Add JH7100 clock generator driver
  dt-bindings: clock: starfive: Add JH7100 bindings
  dt-bindings: clock: starfive: Add JH7100 clock definitions
  dt-bindings: interrupt-controller: Add StarFive JH7100 plic
  dt-bindings: timer: Add StarFive JH7100 clint
  RISC-V: Add StarFive SoC Kconfig option
parents aca48b2d 299e6f78

Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7100 Clock Generator



maintainers:

  - Geert Uytterhoeven <geert@linux-m68k.org>

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7100-clkgen



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Main clock source (25 MHz)

      - description: Application-specific clock source (12-27 MHz)

      - description: RMII reference clock (50 MHz)

      - description: RGMII RX clock (125 MHz)



  clock-names:

    items:

      - const: osc_sys

      - const: osc_aud

      - const: gmac_rmii_ref

      - const: gmac_gr_mii_rxclk



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive-jh7100.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@11800000 {

            compatible = "starfive,jh7100-clkgen";

            reg = <0x11800000 0x10000>;

            clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;

            clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";

            #clock-cells = <1>;

    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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@@ -45,6 +45,7 @@ properties: 
    items:

      - enum:

          - sifive,fu540-c000-plic

          - starfive,jh7100-plic

          - canaan,k210-plic

      - const: sifive,plic-1.0.0

Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7100 Pin Controller Device Tree Bindings



description: |

  Bindings for the JH7100 RISC-V SoC from StarFive Ltd.



  Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]

  and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have

  configurable bias, drive strength, schmitt trigger etc. The SoC has an

  interesting 2-layered approach to pin muxing best illustrated by the diagram

  below.



                          Signal group 0, 1, ... or 6

                                 ___|___

                                |       |

    LCD output -----------------|       |

    CMOS Camera interface ------|       |--- PAD_GPIO[0]

    Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]

      ...                       |       |      ...

                                |       |--- PAD_GPIO[63]

     -------- GPIO0 ------------|       |

    |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]

    | |       |   |             |       |--- PAD_FUNC_SHARE[1]

    | |       |   |  ...        |       |       ...

    | |       |   |             |       |--- PAD_FUNC_SHARE[141]

    | |  -----|---|-- GPIO63 ---|       |

    | | |     |   |   |          -------

    UART0     UART1 --





  The big MUX in the diagram only has 7 different ways of mapping peripherals

  on the left to pins on the right. StarFive calls the 7 configurations "signal

  groups".

  However some peripherals have their I/O go through the 64 "GPIOs". The

  diagram only shows UART0 and UART1, but this also includes a number of other

  UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64

  GPIOs such that any GPIO can be set up to be controlled by any of the

  peripherals.

  Note that signal group 0 doesn't map any of the GPIOs to pins, and only

  signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>

  - Drew Fustini <drew@beagleboard.org>



properties:

  compatible:

    const: starfive,jh7100-pinctrl



  reg:

    minItems: 2

    maxItems: 2



  reg-names:

    items:

      - const: gpio

      - const: padctl



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  gpio-controller: true



  "#gpio-cells":

    const: 2



  interrupts:

    maxItems: 1

    description: The GPIO parent interrupt.



  interrupt-controller: true



  "#interrupt-cells":

    const: 2



  starfive,signal-group:

    description: |

      Select one of the 7 signal groups. If this property is not set it

      defaults to the configuration already chosen by the earlier boot stages.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2, 3, 4, 5, 6]



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - gpio-controller

  - "#gpio-cells"

  - interrupts

  - interrupt-controller

  - "#interrupt-cells"



patternProperties:

  '-[0-9]+$':

    type: object

    patternProperties:

      '-pins$':

        type: object

        description: |

          A pinctrl node should contain at least one subnode representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to

          muxer configuration, bias, input enable/disable, input schmitt

          trigger enable/disable, slew-rate and drive strength.

        $ref: "/schemas/pinctrl/pincfg-node.yaml"



        properties:

          pins:

            description: |

              The list of pin identifiers that properties in the node apply to.

              This should be set using either the PAD_GPIO or PAD_FUNC_SHARE

              macros.

              Either this or "pinmux" has to be specified, but not both.

            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"



          pinmux:

            description: |

              The list of GPIOs and their mux settings that properties in the

              node apply to. This should be set using the GPIOMUX macro.

              Either this or "pins" has to be specified, but not both.

            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"



          bias-disable: true



          bias-pull-up:

            type: boolean



          bias-pull-down:

            type: boolean



          drive-strength:

            enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]



          input-enable: true



          input-disable: true



          input-schmitt-enable: true



          input-schmitt-disable: true



          slew-rate:

            maximum: 7



          starfive,strong-pull-up:

            description: enable strong pull-up.

            type: boolean



        additionalProperties: false



    additionalProperties: false



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive-jh7100.h>

    #include <dt-bindings/reset/starfive-jh7100.h>

    #include <dt-bindings/pinctrl/pinctrl-starfive.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pinctrl@11910000 {

            compatible = "starfive,jh7100-pinctrl";

            reg = <0x0 0x11910000 0x0 0x10000>,

                  <0x0 0x11858000 0x0 0x1000>;

            reg-names = "gpio", "padctl";

            clocks = <&clkgen JH7100_CLK_GPIO_APB>;

            resets = <&clkgen JH7100_RSTN_GPIO_APB>;

            interrupts = <32>;

            gpio-controller;

            #gpio-cells = <2>;

            interrupt-controller;

            #interrupt-cells = <2>;

            starfive,signal-group = <6>;



            gmac_pins_default: gmac-0 {

                gtxclk-pins {

                    pins = <PAD_FUNC_SHARE(115)>;

                    bias-pull-up;

                    drive-strength = <35>;

                    input-enable;

                    input-schmitt-enable;

                    slew-rate = <0>;

                };

                miitxclk-pins {

                    pins = <PAD_FUNC_SHARE(116)>;

                    bias-pull-up;

                    drive-strength = <14>;

                    input-enable;

                    input-schmitt-disable;

                    slew-rate = <0>;

                };

                tx-pins {

                    pins = <PAD_FUNC_SHARE(117)>,

                           <PAD_FUNC_SHARE(119)>,

                           <PAD_FUNC_SHARE(120)>,

                           <PAD_FUNC_SHARE(121)>,

                           <PAD_FUNC_SHARE(122)>,

                           <PAD_FUNC_SHARE(123)>,

                           <PAD_FUNC_SHARE(124)>,

                           <PAD_FUNC_SHARE(125)>,

                           <PAD_FUNC_SHARE(126)>;

                    bias-disable;

                    drive-strength = <35>;

                    input-disable;

                    input-schmitt-disable;

                    slew-rate = <0>;

                };

                rxclk-pins {

                    pins = <PAD_FUNC_SHARE(127)>;

                    bias-pull-up;

                    drive-strength = <14>;

                    input-enable;

                    input-schmitt-disable;

                    slew-rate = <6>;

                };

                rxer-pins {

                    pins = <PAD_FUNC_SHARE(129)>;

                    bias-pull-up;

                    drive-strength = <14>;

                    input-enable;

                    input-schmitt-disable;

                    slew-rate = <0>;

                };

                rx-pins {

                    pins = <PAD_FUNC_SHARE(128)>,

                           <PAD_FUNC_SHARE(130)>,

                           <PAD_FUNC_SHARE(131)>,

                           <PAD_FUNC_SHARE(132)>,

                           <PAD_FUNC_SHARE(133)>,

                           <PAD_FUNC_SHARE(134)>,

                           <PAD_FUNC_SHARE(135)>,

                           <PAD_FUNC_SHARE(136)>,

                           <PAD_FUNC_SHARE(137)>,

                           <PAD_FUNC_SHARE(138)>,

                           <PAD_FUNC_SHARE(139)>,

                           <PAD_FUNC_SHARE(140)>,

                           <PAD_FUNC_SHARE(141)>;

                    bias-pull-up;

                    drive-strength = <14>;

                    input-enable;

                    input-schmitt-enable;

                    slew-rate = <0>;

                };

            };



            i2c0_pins_default: i2c0-0 {

                i2c-pins {

                    pinmux = <GPIOMUX(62, GPO_LOW,

                              GPO_I2C0_PAD_SCK_OEN,

                              GPI_I2C0_PAD_SCK_IN)>,

                             <GPIOMUX(61, GPO_LOW,

                              GPO_I2C0_PAD_SDA_OEN,

                              GPI_I2C0_PAD_SDA_IN)>;

                    bias-disable; /* external pull-up */

                    input-enable;

                    input-schmitt-enable;

                };

            };



            uart3_pins_default: uart3-0 {

                rx-pins {

                    pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,

                              GPI_UART3_PAD_SIN)>;

                    bias-pull-up;

                    input-enable;

                    input-schmitt-enable;

                };

                tx-pins {

                    pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,

                              GPO_ENABLE, GPI_NONE)>;

                    bias-disable;

                    input-disable;

                    input-schmitt-disable;

                };

            };

        };



        gmac {

            pinctrl-0 = <&gmac_pins_default>;

            pinctrl-names = "default";

        };



        i2c0 {

            pinctrl-0 = <&i2c0_pins_default>;

            pinctrl-names = "default";

        };



        uart3 {

            pinctrl-0 = <&uart3_pins_default>;

            pinctrl-names = "default";

        };

    };



...

Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7100 SoC Reset Controller Device Tree Bindings



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    enum:

      - starfive,jh7100-reset



  reg:

    maxItems: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    reset-controller@11840000 {

        compatible = "starfive,jh7100-reset";

        reg = <0x11840000 0x10000>;

        #reset-cells = <1>;

    };



...

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml

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@@ -40,6 +40,11 @@ properties: 
              - brcm,bcm11351-dw-apb-uart

              - brcm,bcm21664-dw-apb-uart

          - const: snps,dw-apb-uart

      - items:

          - enum:

              - starfive,jh7100-hsuart

              - starfive,jh7100-uart

          - const: snps,dw-apb-uart

      - const: snps,dw-apb-uart



  reg: