Commit bb58d1ae authored by Joel Fernandes's avatar Joel Fernandes Committed by Alexandre Courbot
Browse files

gpu: nova-core: falcon: Add support to check if RISC-V is active 



Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.

Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
Signed-off-by: default avatarJoel Fernandes <joelagnelf@nvidia.com>
Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com>
parent 19b0a6e7

drivers/gpu/nova-core/falcon.rs

+9 −0
Original line number Diff line number Diff line
@@ -612,4 +612,13 @@ pub(crate) fn signature_reg_fuse_version( 
        self.hal

            .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id)

    }



    /// Check if the RISC-V core is active.

    ///

    /// Returns `true` if the RISC-V core is active, `false` otherwise.

    #[expect(unused)]

    pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {

        let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID);

        cpuctl.active_stat()

    }

}

drivers/gpu/nova-core/regs.rs

+6 −1
Original line number Diff line number Diff line
@@ -339,7 +339,12 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 


// PRISCV



register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] {

register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] {

    0:0     halted as bool;

    7:7     active_stat as bool;

});



register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] {

    0:0     valid as bool;

    4:4     core_select as bool => PeregrineCoreSelect;

    8:8     br_fetch as bool;