Commit bb5acdea authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
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drm/msm: registers: Add GMU FW version register 



Add a register that contains the GMU core firmware version on non-
legacy (non-sdm845-family) SoCs.

The name is guesstimated based on what it does downstream, but it'll
do.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarAkhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/629932/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent c5fb51b7

drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

+5 −0
Original line number Diff line number Diff line
@@ -52,6 +52,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 
	<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>

	<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>

	<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>

	<reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION">

		<bitfield name="MAJOR" low="28" high="31"/>

		<bitfield name="MINOR" low="16" high="27"/>

		<bitfield name="STEP" low="0" high="15"/>

	</reg32>

	<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>

	<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>

	<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>