Commit bb5db22c authored by Zhang Rui's avatar Zhang Rui Committed by Len Brown
Browse files

tools/power/turbostat: Enable MSR_CORE_C1_RES support for ICX 



Enable Core C1 hardware residency counter (MSR_CORE_C1_RES) on ICX.

Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 17d1ea13

tools/power/x86/turbostat/turbostat.c

+1 −0
Original line number Diff line number Diff line
@@ -664,6 +664,7 @@ static const struct platform_features icx_features = { 
	.bclk_freq = BCLK_100MHZ,

	.supported_cstates = CC1 | CC6 | PC2 | PC6,

	.cst_limit = CST_LIMIT_ICX,

	.has_msr_core_c1_res = 1,

	.has_irtl_msrs = 1,

	.has_cst_prewake_bit = 1,

	.trl_msrs = TRL_BASE | TRL_CORECOUNT,