Commit bb763b5f authored by Aaron Liu's avatar Aaron Liu Committed by Alex Deucher
Browse files

drm/amdgpu: add RLC_PG_DELAY_3 for yellow carp 



RLC_PG_DELAY_3 is to make RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence when CGPG feature is enabled.

Signed-off-by: default avatarAaron Liu <aaron.liu@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c16e87d6

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −5
Original line number Diff line number Diff line
@@ -8064,12 +8064,23 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 
	 * in refclk count. Note that RLC FW is modified to take 16 bits from

	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.

	 *

	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)

	 * as part of CGPG enablement starting point.

	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)

	 * of CGPG enablement starting point.

	 * Power/performance team will optimize it and might give a new value later.

	 */

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

		switch (adev->asic_type) {

		case CHIP_VANGOGH:

			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;

			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);

			break;

		case CHIP_YELLOW_CARP:

			data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;

			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);

			break;

		default:

			break;

		}

	}

}