Commit bb87e511 authored by Ilpo Järvinen's avatar Ilpo Järvinen Committed by Alex Deucher
Browse files

drm/amdgpu: Use RMW accessors for changing LNKCTL2 



Convert open coded RMW accesses for LNKCTL2 to use
pcie_capability_clear_and_set_word() which makes its easier to
understand what the code tries to do.

LNKCTL2 is not really owned by any driver because it is a collection of
control bits that PCI core might need to touch. RMW accessors already
have support for proper locking for a selected set of registers
(LNKCTL2 is not yet among them but likely will be in the future) to
avoid losing concurrent updates.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Suggested-by: default avatarLukas Wunner <lukas@wunner.de>
Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a5fc4e50

drivers/gpu/drm/amd/amdgpu/cik.c

+15 −26
Original line number Diff line number Diff line
@@ -1638,28 +1638,18 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
								   PCI_EXP_LNKCTL_HAWD);



				/* linkctl2 */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,

								   PCI_EXP_LNKCTL2_ENTER_COMP |

								   PCI_EXP_LNKCTL2_TX_MARGIN,

								   bridge_cfg2 &

								   (PCI_EXP_LNKCTL2_ENTER_COMP |

								    PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,

								   PCI_EXP_LNKCTL2_ENTER_COMP |

								   PCI_EXP_LNKCTL2_TX_MARGIN,

								   gpu_cfg2 &

								   (PCI_EXP_LNKCTL2_ENTER_COMP |

								    PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);

				tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1674,16 +1664,15 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
	speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;

	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);



	pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;



	tmp16 = 0;

	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);

	pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,

					   PCI_EXP_LNKCTL2_TLS, tmp16);



	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);

	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;

drivers/gpu/drm/amd/amdgpu/si.c

+15 −26
Original line number Diff line number Diff line
@@ -2331,28 +2331,18 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
								   gpu_cfg &

								   PCI_EXP_LNKCTL_HAWD);



				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,

								   PCI_EXP_LNKCTL2_ENTER_COMP |

								   PCI_EXP_LNKCTL2_TX_MARGIN,

								   bridge_cfg2 &

								   (PCI_EXP_LNKCTL2_ENTER_COMP |

								    PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,

								   PCI_EXP_LNKCTL2_ENTER_COMP |

								   PCI_EXP_LNKCTL2_TX_MARGIN,

								   gpu_cfg2 &

								   (PCI_EXP_LNKCTL2_ENTER_COMP |

								    PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp &= ~LC_SET_QUIESCE;
@@ -2365,16 +2355,15 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;

	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;



	tmp16 = 0;

	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);

	pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,

					   PCI_EXP_LNKCTL2_TLS, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;