Commit bba38b87 authored by Johan Hovold's avatar Johan Hovold Committed by Alexandre Belloni
Browse files

rtc: pm8xxx: add support for uefi offset 



On many Qualcomm platforms the PMIC RTC control and time registers are
read-only so that the RTC time can not be updated. Instead an offset
needs be stored in some machine-specific non-volatile memory, which the
driver can take into account.

Add support for storing a 32-bit offset from the GPS time epoch in a
UEFI variable so that the RTC time can be set on such platforms.

The UEFI variable is

            882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo

and holds a 12-byte structure where the first four bytes is a GPS time
offset in little-endian byte order.

Note that this format is not arbitrary as the variable is shared with
the UEFI firmware (and Windows).

Tested-by: default avatarJens Glathe <jens.glathe@oldschoolsolutions.biz>
Tested-by: default avatarSteev Klimaszewski <steev@kali.org>
Tested-by: default avatarJoel Stanley <joel@jms.id.au>
Tested-by: Sebastian Reichel <sre@kernel.org> # Lenovo T14s Gen6
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250219134118.31017-3-johan+linaro@kernel.org


Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent 931a8891

drivers/rtc/rtc-pm8xxx.c

+132 −24
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */

#include <linux/efi.h>

#include <linux/of.h>

#include <linux/module.h>

#include <linux/nvmem-consumer.h>
@@ -16,9 +17,10 @@ 
#include <linux/regmap.h>

#include <linux/slab.h>

#include <linux/spinlock.h>



#include <linux/unaligned.h>



#include <asm/byteorder.h>



/* RTC_CTRL register bit fields */

#define PM8xxx_RTC_ENABLE		BIT(7)

#define PM8xxx_RTC_ALARM_CLEAR		BIT(0)
@@ -46,14 +48,21 @@ struct pm8xxx_rtc_regs { 
	unsigned int alarm_en;

};



struct qcom_uefi_rtc_info {

	__le32	offset_gps;

	u8	reserved[8];

} __packed;



/**

 * struct pm8xxx_rtc -  RTC driver internal structure

 * @rtc:		RTC device

 * @regmap:		regmap used to access registers

 * @allow_set_time:	whether the time can be set

 * @use_uefi:		use UEFI variable as fallback for offset

 * @alarm_irq:		alarm irq number

 * @regs:		register description

 * @dev:		device structure

 * @rtc_info:		qcom uefi rtc-info structure

 * @nvmem_cell:		nvmem cell for offset

 * @offset:		offset from epoch in seconds

 */
@@ -61,13 +70,101 @@ struct pm8xxx_rtc { 
	struct rtc_device *rtc;

	struct regmap *regmap;

	bool allow_set_time;

	bool use_uefi;

	int alarm_irq;

	const struct pm8xxx_rtc_regs *regs;

	struct device *dev;

	struct qcom_uefi_rtc_info rtc_info;

	struct nvmem_cell *nvmem_cell;

	u32 offset;

};



#ifdef CONFIG_EFI



MODULE_IMPORT_NS("EFIVAR");



#define QCOM_UEFI_NAME	L"RTCInfo"

#define QCOM_UEFI_GUID	EFI_GUID(0x882f8c2b, 0x9646, 0x435f, \

				 0x8d, 0xe5, 0xf2, 0x08, 0xff, 0x80, 0xc1, 0xbd)

#define QCOM_UEFI_ATTRS	(EFI_VARIABLE_NON_VOLATILE | \

			 EFI_VARIABLE_BOOTSERVICE_ACCESS | \

			 EFI_VARIABLE_RUNTIME_ACCESS)



static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)

{

	struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;

	unsigned long size = sizeof(*rtc_info);

	struct device *dev = rtc_dd->dev;

	efi_status_t status;

	u32 offset_gps;

	int rc;



	rc = efivar_lock();

	if (rc)

		return rc;



	status = efivar_get_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID, NULL,

				     &size, rtc_info);

	efivar_unlock();



	if (status != EFI_SUCCESS) {

		dev_dbg(dev, "failed to read UEFI offset: %lu\n", status);

		return efi_status_to_err(status);

	}



	if (size != sizeof(*rtc_info)) {

		dev_dbg(dev, "unexpected UEFI structure size %lu\n", size);

		return -EINVAL;

	}



	dev_dbg(dev, "uefi_rtc_info = %*ph\n", (int)size, rtc_info);



	/* Convert from GPS to Unix time offset */

	offset_gps = le32_to_cpu(rtc_info->offset_gps);

	rtc_dd->offset = offset_gps + (u32)RTC_TIMESTAMP_EPOCH_GPS;



	return 0;

}



static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)

{

	struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;

	unsigned long size = sizeof(*rtc_info);

	struct device *dev = rtc_dd->dev;

	efi_status_t status;

	u32 offset_gps;



	/* Convert from Unix to GPS time offset */

	offset_gps = offset - (u32)RTC_TIMESTAMP_EPOCH_GPS;



	rtc_info->offset_gps = cpu_to_le32(offset_gps);



	dev_dbg(dev, "efi_rtc_info = %*ph\n", (int)size, rtc_info);



	status = efivar_set_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID,

				     QCOM_UEFI_ATTRS, size, rtc_info);

	if (status != EFI_SUCCESS) {

		dev_dbg(dev, "failed to write UEFI offset: %lx\n", status);

		return efi_status_to_err(status);

	}



	return 0;

}



#else	/* CONFIG_EFI */



static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)

{

	return -ENODEV;

}



static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)

{

	return -ENODEV;

}



#endif	/* CONFIG_EFI */



static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)

{

	size_t len;
@@ -110,14 +207,6 @@ static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset) 
	return 0;

}



static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)

{

	if (!rtc_dd->nvmem_cell)

		return 0;



	return pm8xxx_rtc_read_nvmem_offset(rtc_dd);

}



static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)

{

	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
@@ -155,7 +244,7 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) 
	u32 offset;

	int rc;



	if (!rtc_dd->nvmem_cell)

	if (!rtc_dd->nvmem_cell && !rtc_dd->use_uefi)

		return -ENODEV;



	rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
@@ -167,7 +256,11 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) 
	if (offset == rtc_dd->offset)

		return 0;



	if (rtc_dd->nvmem_cell)

		rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);

	else

		rc = pm8xxx_rtc_write_uefi_offset(rtc_dd, offset);



	if (rc)

		return rc;
@@ -455,6 +548,30 @@ static const struct of_device_id pm8xxx_id_table[] = { 
};

MODULE_DEVICE_TABLE(of, pm8xxx_id_table);



static int pm8xxx_rtc_probe_offset(struct pm8xxx_rtc *rtc_dd)

{

	int rc;



	rtc_dd->nvmem_cell = devm_nvmem_cell_get(rtc_dd->dev, "offset");

	if (IS_ERR(rtc_dd->nvmem_cell)) {

		rc = PTR_ERR(rtc_dd->nvmem_cell);

		if (rc != -ENOENT)

			return rc;

		rtc_dd->nvmem_cell = NULL;

	} else {

		return pm8xxx_rtc_read_nvmem_offset(rtc_dd);

	}



	/* Use UEFI storage as fallback if available */

	if (efivar_is_available()) {

		rc = pm8xxx_rtc_read_uefi_offset(rtc_dd);

		if (rc == 0)

			rtc_dd->use_uefi = true;

	}



	return 0;

}



static int pm8xxx_rtc_probe(struct platform_device *pdev)

{

	const struct of_device_id *match;
@@ -469,6 +586,9 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) 
	if (rtc_dd == NULL)

		return -ENOMEM;



	rtc_dd->regs = match->data;

	rtc_dd->dev = &pdev->dev;



	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);

	if (!rtc_dd->regmap)

		return -ENXIO;
@@ -479,20 +599,8 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) 


	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,

						      "allow-set-time");



	rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");

	if (IS_ERR(rtc_dd->nvmem_cell)) {

		rc = PTR_ERR(rtc_dd->nvmem_cell);

		if (rc != -ENOENT)

			return rc;

		rtc_dd->nvmem_cell = NULL;

	}



	rtc_dd->regs = match->data;

	rtc_dd->dev = &pdev->dev;



	if (!rtc_dd->allow_set_time) {

		rc = pm8xxx_rtc_read_offset(rtc_dd);

		rc = pm8xxx_rtc_probe_offset(rtc_dd);

		if (rc)

			return rc;

	}

include/linux/rtc.h

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ struct rtc_device { 
/* useful timestamps */

#define RTC_TIMESTAMP_BEGIN_0000	-62167219200ULL /* 0000-01-01 00:00:00 */

#define RTC_TIMESTAMP_BEGIN_1900	-2208988800LL /* 1900-01-01 00:00:00 */

#define RTC_TIMESTAMP_EPOCH_GPS		315964800LL /* 1980-01-06 00:00:00 */

#define RTC_TIMESTAMP_BEGIN_2000	946684800LL /* 2000-01-01 00:00:00 */

#define RTC_TIMESTAMP_END_2063		2966371199LL /* 2063-12-31 23:59:59 */

#define RTC_TIMESTAMP_END_2079		3471292799LL /* 2079-12-31 23:59:59 */