Commit bbbfa70d authored by Naladala Ramanaidu's avatar Naladala Ramanaidu Committed by Suraj Kandpal
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drm/i915: Add fallback for CDCLK selection when min_cdclk is too high 



In cases where the requested minimum CDCLK exceeds all available
values for the current reference clock, the CDCLK selection logic
previously returned 0. This could result coverity division or
modulo by zero issue.
Introduce a fallback mechanism that returns platform's max_cdclk_freq
instead of 0.

v2: Update safe fallback value to max cdclk. (Ville)
v3: Update commit messgae (Mika)

Signed-off-by: default avatarNaladala Ramanaidu <ramanaidu.naladala@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20251017150526.781715-1-ramanaidu.naladala@intel.com
parent 938c6c9b

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −1
Original line number Diff line number Diff line
@@ -1561,7 +1561,7 @@ static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 
	drm_WARN(display->drm, 1,

		 "Cannot satisfy minimum cdclk %d with refclk %u\n",

		 min_cdclk, display->cdclk.hw.ref);

	return 0;

	return display->cdclk.max_cdclk_freq;

}



static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)