Unverified Commit bbfbb579 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-drivers-fixes-for-6.12' of... 

Merge tag 'qcom-drivers-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes

Qualcomm driver fixes for v6.12

The Qualcomm EDAC driver's configuration of interrupts is made optional,
to avoid violating security constriants on X Elite platform .

The SCM drivers' detection mechanism for the presence of SHM bridge in QTEE,
is corrected to handle the case where firmware successfully returns that
the interface isn't supported.

The GLINK driver and the PMIC GLINK interface is updated to handle
buffer allocation issues during initialization of the communication
channel.

Allocation error handling in the socinfo dirver is corrected, and then
the fix is corrected.

* tag 'qcom-drivers-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: pmic_glink: Handle GLINK intent allocation rejections
  rpmsg: glink: Handle rejected intent request better
  soc: qcom: socinfo: fix revision check in qcom_socinfo_probe()
  firmware: qcom: scm: Return -EOPNOTSUPP for unsupported SHM bridge enabling
  EDAC/qcom: Make irq configuration optional
  firmware: qcom: scm: fix a NULL-pointer dereference
  firmware: qcom: scm: suppress download mode error
  soc: qcom: Add check devm_kasprintf() returned value
  MAINTAINERS: Qualcomm SoC: Match reserved-memory bindings

Link: https://lore.kernel.org/r/20241101161455.746290-1-andersson@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 566064e5 f8c87919

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -2852,7 +2852,7 @@ F: Documentation/devicetree/bindings/arm/qcom.yaml 
F:	Documentation/devicetree/bindings/bus/qcom*

F:	Documentation/devicetree/bindings/cache/qcom,llcc.yaml

F:	Documentation/devicetree/bindings/firmware/qcom,scm.yaml

F:	Documentation/devicetree/bindings/reserved-memory/qcom

F:	Documentation/devicetree/bindings/reserved-memory/qcom*

F:	Documentation/devicetree/bindings/soc/qcom/

F:	arch/arm/boot/dts/qcom/

F:	arch/arm/configs/qcom_defconfig

drivers/edac/qcom_edac.c

+5 −3
Original line number Diff line number Diff line
@@ -342,9 +342,11 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) 
	int ecc_irq;

	int rc;



	if (!llcc_driv_data->ecc_irq_configured) {

		rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);

		if (rc)

			return rc;

	}



	/* Allocate edac control info */

	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",

drivers/firmware/qcom/qcom_scm.c

+14 −3
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ enum qcom_scm_qseecom_tz_cmd_info { 
};



#define QSEECOM_MAX_APP_NAME_SIZE		64

#define SHMBRIDGE_RESULT_NOTSUPP		4



/* Each bit configures cold/warm boot address for one of the 4 CPUs */

static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
@@ -216,7 +217,7 @@ static DEFINE_SPINLOCK(scm_query_lock); 


struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void)

{

	return __scm->mempool;

	return __scm ? __scm->mempool : NULL;

}



static enum qcom_scm_convention __get_convention(void)
@@ -545,7 +546,7 @@ static void qcom_scm_set_download_mode(u32 dload_mode) 
	} else if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT,

						QCOM_SCM_BOOT_SET_DLOAD_MODE)) {

		ret = __qcom_scm_set_dload_mode(__scm->dev, !!dload_mode);

	} else {

	} else if (dload_mode) {

		dev_err(__scm->dev,

			"No available mechanism for setting download mode\n");

	}
@@ -1361,6 +1362,8 @@ EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available); 


int qcom_scm_shm_bridge_enable(void)

{

	int ret;



	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_SHM_BRIDGE_ENABLE,
@@ -1373,7 +1376,15 @@ int qcom_scm_shm_bridge_enable(void) 
					  QCOM_SCM_MP_SHM_BRIDGE_ENABLE))

		return -EOPNOTSUPP;



	return qcom_scm_call(__scm->dev, &desc, &res) ?: res.result[0];

	ret = qcom_scm_call(__scm->dev, &desc, &res);



	if (ret)

		return ret;



	if (res.result[0] == SHMBRIDGE_RESULT_NOTSUPP)

		return -EOPNOTSUPP;



	return res.result[0];

}

EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_enable);

drivers/rpmsg/qcom_glink_native.c

+7 −3
Original line number Diff line number Diff line
@@ -1440,14 +1440,18 @@ static int qcom_glink_request_intent(struct qcom_glink *glink, 
		goto unlock;



	ret = wait_event_timeout(channel->intent_req_wq,

				 READ_ONCE(channel->intent_req_result) >= 0 &&

				 READ_ONCE(channel->intent_received),

				 READ_ONCE(channel->intent_req_result) == 0 ||

				 (READ_ONCE(channel->intent_req_result) > 0 &&

				  READ_ONCE(channel->intent_received)) ||

				 glink->abort_tx,

				 10 * HZ);

	if (!ret) {

		dev_err(glink->dev, "intent request timed out\n");

		ret = -ETIMEDOUT;

	} else if (glink->abort_tx) {

		ret = -ECANCELED;

	} else {

		ret = READ_ONCE(channel->intent_req_result) ? 0 : -ECANCELED;

		ret = READ_ONCE(channel->intent_req_result) ? 0 : -EAGAIN;

	}



unlock:

drivers/soc/qcom/llcc-qcom.c

+3 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ struct qcom_llcc_config { 
	int size;

	bool need_llcc_cfg;

	bool no_edac;

	bool irq_configured;

};



struct qcom_sct_config {
@@ -718,6 +719,7 @@ static const struct qcom_llcc_config x1e80100_cfg[] = { 
		.need_llcc_cfg	= true,

		.reg_offset	= llcc_v2_1_reg_offset,

		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,

		.irq_configured = true,

	},

};
@@ -1345,6 +1347,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) 
	drv_data->cfg = llcc_cfg;

	drv_data->cfg_size = sz;

	drv_data->edac_reg_offset = cfg->edac_reg_offset;

	drv_data->ecc_irq_configured = cfg->irq_configured;

	mutex_init(&drv_data->lock);

	platform_set_drvdata(pdev, drv_data);