Commit bc6397cf authored by K Prateek Nayak's avatar K Prateek Nayak Committed by Ingo Molnar
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x86/cpu/topology: Define AMD64_CPUID_EXT_FEAT MSR 



Add defines for the 0xc001_1005 MSR (Core::X86::Msr::CPUID_ExtFeatures) used
to toggle the extended CPUID features, instead of using literal numbers. Also
define and use the bits necessary for an old TOPOEXT fixup on AMD Family 0x15
processors.

No functional changes intended.

  [ bp: Massage, rename MSR to adhere to the documentation name. ]

Signed-off-by: default avatarK Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/20250901170418.4314-1-kprateek.nayak@amd.com
parent d691c5f8

arch/x86/include/asm/msr-index.h

+5 −0
Original line number Diff line number Diff line
@@ -631,6 +631,11 @@ 
#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_CPUID_FN_7		0xc0011002

#define MSR_AMD64_CPUID_FN_1		0xc0011004



#define MSR_AMD64_CPUID_EXT_FEAT	0xc0011005

#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT	54

#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT	BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)



#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_TW_CFG		0xc0011023

arch/x86/kernel/cpu/topology_amd.c

+4 −3
Original line number Diff line number Diff line
@@ -163,11 +163,12 @@ static void topoext_fixup(struct topo_scan *tscan) 
	    c->x86 != 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f)

		return;



	if (msr_set_bit(0xc0011005, 54) <= 0)

	if (msr_set_bit(MSR_AMD64_CPUID_EXT_FEAT,

			MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT) <= 0)

		return;



	rdmsrq(0xc0011005, msrval);

	if (msrval & BIT_64(54)) {

	rdmsrq(MSR_AMD64_CPUID_EXT_FEAT, msrval);

	if (msrval & MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT) {

		set_cpu_cap(c, X86_FEATURE_TOPOEXT);

		pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");

	}