Blackfin arch: update to latest anomaly sheets

/*

 * File: include/asm-blackfin/mach-bf527/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2007 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */

/* This file shoule be up to date with:

 *  - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List

 */

#ifndef _MACH_ANOMALY_H_

#define _MACH_ANOMALY_H_

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */

#define ANOMALY_05000074 (1)

/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */

#define ANOMALY_05000119 (1)

/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */

#define ANOMALY_05000122 (1)

/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */

#define ANOMALY_05000301 (1)

/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

#define ANOMALY_05000312 (1)

/* Incorrect Access of OTP_STATUS During otp_write() Function */

#define ANOMALY_05000328 (1)

/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */

#define ANOMALY_05000337 (1)

/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */

#define ANOMALY_05000342 (1)

/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */

#define ANOMALY_05000347 (1)

#endif

#define ANOMALY_05000122 (1)

/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */

#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)

/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/

#define ANOMALY_05000166 (1)	/* XXX: deleted from BF537 sheet ? */

/* PPI_DELAY not functional in PPI modes with 0 frame syncs */

#define ANOMALY_05000180 (1)

/* Instruction Cache Is Not Functional */

 */

/* This file shoule be up to date with:

 *  - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List

 *  - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List

 */

#ifndef _MACH_ANOMALY_H_

#define ANOMALY_05000122 (1)

/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */

#define ANOMALY_05000255 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */

#define ANOMALY_05000272 (1)

/* False Hardware Error Exception when ISR context is not restored */

#define ANOMALY_05000281 (1)

/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */

#define ANOMALY_05000304 (1)

/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */

#define ANOMALY_05000310 (1)

/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

#define ANOMALY_05000337 (1)

/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */

#define ANOMALY_05000338 (1)

/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */

#define ANOMALY_05000340 (1)

/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */

#define ANOMALY_05000344 (1)

/* USB Calibration Value Is Not Intialized */

#define ANOMALY_05000346 (1)

/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */

#define ANOMALY_05000347 (1)

/* Data Lost when Core Reads SDH Data FIFO */

#define ANOMALY_05000349 (1)

/* PLL Status Register Is Inaccurate */

#define ANOMALY_05000351 (1)

/* Anomalies that don't exist on this proc */

#define ANOMALY_05000125 (0)

#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)

/* Anomalies that don't exist on this proc */

#define ANOMALY_05000158 (0)

#define ANOMALY_05000183 (0)

#define ANOMALY_05000273 (0)

#define ANOMALY_05000311 (0)