Commit bca20e6a authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'nand/for-5.16' into mtd/next 

Core:
* Remove obsolete macros only used by the old nand_ecclayout struct
* MAINTAINERS: Add entry for Qualcomm NAND controller driver

Raw NAND controller drivers:
* Arasan:
  - Prevent an unsupported configuration
* Xway, Socrates: plat_nand, Pasemi, Orion, mpc5121, GPIO, Au1550nd, AMS-Delta:
  - Keep the driver compatible with on-die ECC engines
* cs553x, lpc32xx_slc, ndfc, sharpsl, tmio, txx9ndfmc:
  - Revert the commits: "Fix external use of SW Hamming ECC helper"
  - And let callers use the bare Hamming helpers
* Fsmc: Fix use of SM ORDER
* Intel:
  - Fix potential buffer overflow in probe
* xway, vf610, txx9ndfm, tegra, stm32, plat_nand, oxnas, omap, mtk, hisi504,
  gpmi, gpio, denali, bcm6368, atmel:
  - Make use of the helper function devm_platform_ioremap_resource{,byname}()

Onenand driver:
* Samsung: Drop Exynos4 and describe driver in KConfig

Raw NAND chip drivers:
* Hynix: Add support for H27UCG8T2ETR-BC MLC NAND
parents c13de238 fc9e18f9

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -15571,6 +15571,14 @@ S: Maintained 
F:	Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml

F:	drivers/regulator/vqmmc-ipq4019-regulator.c









QUALCOMM NAND CONTROLLER DRIVER









M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>









L:	linux-mtd@lists.infradead.org









L:	linux-arm-msm@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/mtd/qcom,nandc.yaml









F:	drivers/mtd/nand/raw/qcom_nandc.c

















QUALCOMM RMNET DRIVER









M:	Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>









M:	Sean Tranchetti <stranche@codeaurora.org>
































drivers/mtd/nand/ecc-sw-hamming.c



+4
−3






























Original line number
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Diff line







@@ -364,9 +364,9 @@ int nand_ecc_sw_hamming_calculate(struct nand_device *nand,







{









	struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv;









	unsigned int step_size = nand->ecc.ctx.conf.step_size;









	bool sm_order = engine_conf ? engine_conf->sm_order : false;



















	return ecc_sw_hamming_calculate(buf, step_size, code,









					engine_conf->sm_order);









	return ecc_sw_hamming_calculate(buf, step_size, code, sm_order);









}









EXPORT_SYMBOL(nand_ecc_sw_hamming_calculate);


















@@ -457,9 +457,10 @@ int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf,







{









	struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv;









	unsigned int step_size = nand->ecc.ctx.conf.step_size;









	bool sm_order = engine_conf ? engine_conf->sm_order : false;



















	return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc, step_size,









				      engine_conf->sm_order);









				      sm_order);









}









EXPORT_SYMBOL(nand_ecc_sw_hamming_correct);










































drivers/mtd/nand/onenand/Kconfig



+5
−4






























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Diff line







@@ -33,11 +33,12 @@ config MTD_ONENAND_OMAP2

















config MTD_ONENAND_SAMSUNG









	tristate "OneNAND on Samsung SOC controller support"









	depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4 || COMPILE_TEST









	depends on ARCH_S3C64XX || ARCH_S5PV210 || COMPILE_TEST









	help









	  Support for a OneNAND flash device connected to an Samsung SOC.









	  S3C64XX uses command mapping method.









	  S5PC110/S5PC210 use generic OneNAND method.









	  Support for a OneNAND flash device connected to Samsung S3C64XX









	  (using command mapping method) and S5PC110/S5PC210 (using generic









	  OneNAND method) SoCs.









	  Choose Y here only if you build for such Samsung SoC.



















config MTD_ONENAND_OTP









	bool "OneNAND OTP Support"
































drivers/mtd/nand/raw/ams-delta.c



+9
−3






























Original line number
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Diff line







@@ -217,9 +217,8 @@ static int gpio_nand_setup_interface(struct nand_chip *this, int csline,

















static int gpio_nand_attach_chip(struct nand_chip *chip)









{









	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;



















	if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)









	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&









	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)









		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;



















	return 0;








@@ -370,6 +369,13 @@ static int gpio_nand_probe(struct platform_device *pdev)







	/* Release write protection */









	gpiod_set_value(priv->gpiod_nwp, 0);



















	/*









	 * This driver assumes that the default ECC engine should be TYPE_SOFT.









	 * Set ->engine_type before registering the NAND devices in order to









	 * provide a driver specific default value.









	 */









	this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;



















	/* Scan to find existence of the device */









	err = nand_scan(this, 1);









	if (err)
































drivers/mtd/nand/raw/arasan-nand-controller.c



+15
−0






























Original line number
Diff line number
Diff line







@@ -973,6 +973,21 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,







		nvddr = nand_get_nvddr_timings(conf);









		if (IS_ERR(nvddr))









			return PTR_ERR(nvddr);



















		/*









		 * The controller only supports data payload requests which are









		 * a multiple of 4. In practice, most data accesses are 4-byte









		 * aligned and this is not an issue. However, rounding up will









		 * simply be refused by the controller if we reached the end of









		 * the device *and* we are using the NV-DDR interface(!). In









		 * this situation, unaligned data requests ending at the device









		 * boundary will confuse the controller and cannot be performed.









		 *









		 * This is something that happens in nand_read_subpage() when









		 * selecting software ECC support and must be avoided.









		 */









		if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT)









			return -ENOTSUPP;









	} else {









		sdr = nand_get_sdr_timings(conf);









		if (IS_ERR(sdr))