Unverified Commit bcc87900 authored by Palmer Dabbelt's avatar Palmer Dabbelt
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RISC-V: Document that V registers are clobbered on syscalls 



This is included in the ISA manual, but it's pretty common for bits of
the ISA manual that are actually ABI to change.  So let's document it
explicitly.

Reviewed-by: default avatarBjörn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230619190142.26498-1-palmer@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 533925cb

Documentation/riscv/vector.rst

+8 −0
Original line number Diff line number Diff line
@@ -130,3 +130,11 @@ processes in form of sysctl knob: 


    Modifying the system default enablement status does not affect the enablement

    status of any existing process of thread that do not make an execve() call.



3.  Vector Register State Across System Calls

---------------------------------------------



As indicated by version 1.0 of the V extension [1], vector registers are

clobbered by system calls.



1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc