Commit bcccdf8b authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/apic/uv: Remove the private leaf 0xb parser 



The package shift has been already evaluated by the early CPU init.

Put the mindless copy right next to the original leaf 0xb parser.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarJuergen Gross <jgross@suse.com>
Tested-by: default avatarSohil Mehta <sohil.mehta@intel.com>
Tested-by: default avatarMichael Kelley <mhklinux@outlook.com>
Tested-by: default avatarZhang Rui <rui.zhang@intel.com>
Tested-by: default avatarWang Wendy <wendy.wang@intel.com>
Tested-by: default avatarK Prateek Nayak <kprateek.nayak@amd.com>
Link: https://lore.kernel.org/r/20240212153625.637385562@linutronix.de
parent d5474e4d

arch/x86/include/asm/topology.h

+5 −0
Original line number Diff line number Diff line
@@ -126,6 +126,11 @@ static inline unsigned int topology_get_domain_size(enum x86_topology_domains do 
	return x86_topo_system.dom_size[dom];

}



static inline unsigned int topology_get_domain_shift(enum x86_topology_domains dom)

{

	return dom == TOPO_SMT_DOMAIN ? 0 : x86_topo_system.dom_shifts[dom - 1];

}



extern const struct cpumask *cpu_coregroup_mask(int cpu);

extern const struct cpumask *cpu_clustergroup_mask(int cpu);

arch/x86/kernel/apic/x2apic_uv_x.c

+9 −43
Original line number Diff line number Diff line
@@ -241,55 +241,21 @@ static void __init uv_tsc_check_sync(void) 
	is_uv(UV3) ? sname.s3.field :		\

	undef)



/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */



#define SMT_LEVEL			0	/* Leaf 0xb SMT level */

#define INVALID_TYPE			0	/* Leaf 0xb sub-leaf types */

#define SMT_TYPE			1

#define CORE_TYPE			2

#define LEAFB_SUBTYPE(ecx)		(((ecx) >> 8) & 0xff)

#define BITS_SHIFT_NEXT_LEVEL(eax)	((eax) & 0x1f)



static void set_x2apic_bits(void)

static void __init early_get_apic_socketid_shift(void)

{

	unsigned int eax, ebx, ecx, edx, sub_index;

	unsigned int sid_shift;



	cpuid(0, &eax, &ebx, &ecx, &edx);

	if (eax < 0xb) {

		pr_info("UV: CPU does not have CPUID.11\n");

		return;

	}

	unsigned int sid_shift = topology_get_domain_shift(TOPO_PKG_DOMAIN);



	cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);

	if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {

		pr_info("UV: CPUID.11 not implemented\n");

		return;

	}



	sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);

	sub_index = 1;

	do {

		cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);

		if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {

			sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);

			break;

		}

		sub_index++;

	} while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);

	if (is_uv2_hub() || is_uv3_hub())

		uvh_apicid.v = uv_early_read_mmr(UVH_APICID);



	if (sid_shift) {

		uv_cpuid.apicid_shift	= 0;

		uv_cpuid.apicid_mask	= (~(-1 << sid_shift));

		uv_cpuid.socketid_shift = sid_shift;

	} else {

		pr_info("UV: CPU does not have valid CPUID.11\n");

	}



static void __init early_get_apic_socketid_shift(void)

{

	if (is_uv2_hub() || is_uv3_hub())

		uvh_apicid.v = uv_early_read_mmr(UVH_APICID);



	set_x2apic_bits();



	pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);

	pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);

}