Commit bd3755c1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.11-2024-08-28' of... 

Merge tag 'amd-drm-fixes-6.11-2024-08-28' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.11-2024-08-28:

amdgpu:
- SWSMU gaming stability fix
- SMU 13.0.7 fix
- SWSMU documentation alignment fix
- SMU 14.0.x fixes
- GC 12.x fix
- Display fix
- IP discovery fix
- SMU 13.0.6 fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240828184908.125387-1-alexander.deucher@amd.com
parents 5be63fc1 849f0d58

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+11 −0
Original line number Diff line number Diff line
@@ -1500,6 +1500,7 @@ union gc_info { 
	struct gc_info_v1_0 v1;

	struct gc_info_v1_1 v1_1;

	struct gc_info_v1_2 v1_2;

	struct gc_info_v1_3 v1_3;

	struct gc_info_v2_0 v2;

	struct gc_info_v2_1 v2_1;

};
@@ -1558,6 +1559,16 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 
			adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);

			adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);

		}

		if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {

			adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);

			adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);

			adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);

			adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);

			adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);

			adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);

			adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);

			adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);

		}

		break;

	case 2:

		adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+6 −0
Original line number Diff line number Diff line
@@ -240,6 +240,12 @@ struct amdgpu_gfx_config { 
	uint32_t gc_tcp_size_per_cu;

	uint32_t gc_num_cu_per_sqc;

	uint32_t gc_tcc_size;

	uint32_t gc_tcp_cache_line_size;

	uint32_t gc_instruction_cache_size_per_sqc;

	uint32_t gc_instruction_cache_line_size;

	uint32_t gc_scalar_data_cache_size_per_sqc;

	uint32_t gc_scalar_data_cache_line_size;

	uint32_t gc_tcc_cache_line_size;

};



struct amdgpu_cu_info {

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+1 −1
Original line number Diff line number Diff line
@@ -3005,7 +3005,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
			    (order_base_2(prop->queue_size / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c

+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 
	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |=

			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);



	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

+7 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <drm/drm_blend.h>

#include <drm/drm_gem_atomic_helper.h>

#include <drm/drm_plane_helper.h>

#include <drm/drm_gem_framebuffer_helper.h>

#include <drm/drm_fourcc.h>



#include "amdgpu.h"
@@ -935,10 +936,14 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, 
	}



	afb = to_amdgpu_framebuffer(new_state->fb);

	obj = new_state->fb->obj[0];

	obj = drm_gem_fb_get_obj(new_state->fb, 0);

	if (!obj) {

		DRM_ERROR("Failed to get obj from framebuffer\n");

		return -EINVAL;

	}



	rbo = gem_to_amdgpu_bo(obj);

	adev = amdgpu_ttm_adev(rbo->tbo.bdev);



	r = amdgpu_bo_reserve(rbo, true);

	if (r) {

		dev_err(adev->dev, "fail to reserve bo (%d)\n", r);