Commit bd4d1856 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: convert VLV IOSF SB interface to struct drm_device 



With users both in i915 core and display, struct drm_device is the
common denominator for the VLV IOSF SB users. Also use drm_device for
the helpers on the display side to keep the static inlines as simple as
possible.

We can drop a number of dependencies on i915_drv.h with this.

v2,v3: Rebase

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/c1d013ed88ce2e3e5bdc15ce3bf01a3960b1e817.1747061743.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 8393253b

drivers/gpu/drm/i915/display/i9xx_wm.c

+16 −19
Original line number Diff line number Diff line
@@ -107,43 +107,41 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *dis 


static void chv_set_memory_dvfs(struct intel_display *display, bool enable)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	u32 val;



	vlv_punit_get(dev_priv);

	vlv_punit_get(display->drm);



	val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

	val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

	if (enable)

		val &= ~FORCE_DDR_HIGH_FREQ;

	else

		val |= FORCE_DDR_HIGH_FREQ;

	val &= ~FORCE_DDR_LOW_FREQ;

	val |= FORCE_DDR_FREQ_REQ_ACK;

	vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);

	vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);



	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &

	if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &

		      FORCE_DDR_FREQ_REQ_ACK) == 0, 3))

		drm_err(display->drm,

			"timed out waiting for Punit DDR DVFS request\n");



	vlv_punit_put(dev_priv);

	vlv_punit_put(display->drm);

}



static void chv_set_memory_pm5(struct intel_display *display, bool enable)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	u32 val;



	vlv_punit_get(dev_priv);

	vlv_punit_get(display->drm);



	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

	if (enable)

		val |= DSP_MAXFIFO_PM5_ENABLE;

	else

		val &= ~DSP_MAXFIFO_PM5_ENABLE;

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);

	vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);



	vlv_punit_put(dev_priv);

	vlv_punit_put(display->drm);

}



#define FW_WM(value, plane) \
@@ -3900,7 +3898,6 @@ static void g4x_wm_sanitize(struct intel_display *display) 


static void vlv_wm_get_hw_state(struct intel_display *display)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	struct vlv_wm_values *wm = &display->wm.vlv;

	struct intel_crtc *crtc;

	u32 val;
@@ -3911,9 +3908,9 @@ static void vlv_wm_get_hw_state(struct intel_display *display) 
	wm->level = VLV_WM_LEVEL_PM2;



	if (display->platform.cherryview) {

		vlv_punit_get(dev_priv);

		vlv_punit_get(display->drm);



		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

		val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

		if (val & DSP_MAXFIFO_PM5_ENABLE)

			wm->level = VLV_WM_LEVEL_PM5;
@@ -3926,23 +3923,23 @@ static void vlv_wm_get_hw_state(struct intel_display *display) 
		 * HIGH/LOW bits so that we don't actually change

		 * the current state.

		 */

		val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

		val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

		val |= FORCE_DDR_FREQ_REQ_ACK;

		vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);

		vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);



		if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &

		if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &

			      FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {

			drm_dbg_kms(display->drm,

				    "Punit not acking DDR DVFS request, "

				    "assuming DDR DVFS is disabled\n");

			display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1;

		} else {

			val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

			val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

			if ((val & FORCE_DDR_HIGH_FREQ) == 0)

				wm->level = VLV_WM_LEVEL_DDR_DVFS;

		}



		vlv_punit_put(dev_priv);

		vlv_punit_put(display->drm);

	}



	for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_cdclk.c

+21 −26
Original line number Diff line number Diff line
@@ -567,20 +567,18 @@ static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 
static void vlv_get_cdclk(struct intel_display *display,

			  struct intel_cdclk_config *cdclk_config)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	u32 val;



	vlv_iosf_sb_get(dev_priv,

			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));

	vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));



	cdclk_config->vco = vlv_get_hpll_vco(dev_priv);

	cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",

	cdclk_config->vco = vlv_get_hpll_vco(display->drm);

	cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",

						CCK_DISPLAY_CLOCK_CONTROL,

						cdclk_config->vco);



	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);



	vlv_iosf_sb_put(dev_priv,

	vlv_iosf_sb_put(display->drm,

			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));



	if (display->platform.valleyview)
@@ -658,16 +656,16 @@ static void vlv_set_cdclk(struct intel_display *display, 
	 */

	wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);



	vlv_iosf_sb_get(dev_priv,

	vlv_iosf_sb_get(display->drm,

			BIT(VLV_IOSF_SB_CCK) |

			BIT(VLV_IOSF_SB_BUNIT) |

			BIT(VLV_IOSF_SB_PUNIT));



	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

	val &= ~DSPFREQGUAR_MASK;

	val |= (cmd << DSPFREQGUAR_SHIFT);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &

	vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) &

		      DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),

		     50)) {

		drm_err(display->drm,
@@ -681,12 +679,12 @@ static void vlv_set_cdclk(struct intel_display *display, 
					    cdclk) - 1;



		/* adjust cdclk divider */

		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);

		val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL);

		val &= ~CCK_FREQUENCY_VALUES;

		val |= divider;

		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);

		vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);



		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &

		if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) &

			      CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),

			     50))

			drm_err(display->drm,
@@ -694,7 +692,7 @@ static void vlv_set_cdclk(struct intel_display *display, 
	}



	/* adjust self-refresh exit latency value */

	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);

	val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC);

	val &= ~0x7f;



	/*
@@ -705,9 +703,9 @@ static void vlv_set_cdclk(struct intel_display *display, 
		val |= 4500 / 250; /* 4.5 usec */

	else

		val |= 3000 / 250; /* 3.0 usec */

	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);

	vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val);



	vlv_iosf_sb_put(dev_priv,

	vlv_iosf_sb_put(display->drm,

			BIT(VLV_IOSF_SB_CCK) |

			BIT(VLV_IOSF_SB_BUNIT) |

			BIT(VLV_IOSF_SB_PUNIT));
@@ -723,7 +721,6 @@ static void chv_set_cdclk(struct intel_display *display, 
			  const struct intel_cdclk_config *cdclk_config,

			  enum pipe pipe)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	int cdclk = cdclk_config->cdclk;

	u32 val, cmd = cdclk_config->voltage_level;

	intel_wakeref_t wakeref;
@@ -747,19 +744,19 @@ static void chv_set_cdclk(struct intel_display *display, 
	 */

	wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);



	vlv_punit_get(dev_priv);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	vlv_punit_get(display->drm);

	val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

	val &= ~DSPFREQGUAR_MASK_CHV;

	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &

	vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) &

		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),

		     50)) {

		drm_err(display->drm,

			"timed out waiting for CDclk change\n");

	}



	vlv_punit_put(dev_priv);

	vlv_punit_put(display->drm);



	intel_update_cdclk(display);
@@ -3528,10 +3525,8 @@ static int pch_rawclk(struct intel_display *display) 


static int vlv_hrawclk(struct intel_display *display)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	/* RAWCLK_FREQ_VLV register updated from power well code */

	return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",

	return vlv_get_cck_clock_hpll(display->drm, "hrawclk",

				      CCK_DISPLAY_REF_CLOCK_CONTROL);

}

drivers/gpu/drm/i915/display/intel_display.c

+12 −11
Original line number Diff line number Diff line
@@ -140,46 +140,47 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, 
			      const struct intel_crtc_state *crtc_state);



/* returns HPLL frequency in kHz */

int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)

int vlv_get_hpll_vco(struct drm_device *drm)

{

	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };



	/* Obtain SKU information */

	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &

	hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &

		CCK_FUSE_HPLL_FREQ_MASK;



	return vco_freq[hpll_freq] * 1000;

}



int vlv_get_cck_clock(struct drm_i915_private *dev_priv,

int vlv_get_cck_clock(struct drm_device *drm,

		      const char *name, u32 reg, int ref_freq)

{

	u32 val;

	int divider;



	val = vlv_cck_read(dev_priv, reg);

	val = vlv_cck_read(drm, reg);

	divider = val & CCK_FREQUENCY_VALUES;



	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=

	drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=

		 (divider << CCK_FREQUENCY_STATUS_SHIFT),

		 "%s change in progress\n", name);



	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);

}



int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,

int vlv_get_cck_clock_hpll(struct drm_device *drm,

			   const char *name, u32 reg)

{

	struct drm_i915_private *dev_priv = to_i915(drm);

	int hpll;



	vlv_cck_get(dev_priv);

	vlv_cck_get(drm);



	if (dev_priv->hpll_freq == 0)

		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);

		dev_priv->hpll_freq = vlv_get_hpll_vco(drm);



	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);

	hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq);



	vlv_cck_put(dev_priv);

	vlv_cck_put(drm);



	return hpll;

}
@@ -191,7 +192,7 @@ void intel_update_czclk(struct intel_display *display) 
	if (!display->platform.valleyview && !display->platform.cherryview)

		return;



	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",

	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(display->drm, "czclk",

						      CCK_CZ_CLOCK_CONTROL);



	drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);

drivers/gpu/drm/i915/display/intel_display.h

+3 −4
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ struct drm_encoder; 
struct drm_file;

struct drm_format_info;

struct drm_framebuffer;

struct drm_i915_private;

struct drm_mode_fb_cmd2;

struct drm_modeset_acquire_ctx;

struct drm_plane;
@@ -452,10 +451,10 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 
void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);

void i830_enable_pipe(struct intel_display *display, enum pipe pipe);

void i830_disable_pipe(struct intel_display *display, enum pipe pipe);

int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);

int vlv_get_cck_clock(struct drm_i915_private *dev_priv,

int vlv_get_hpll_vco(struct drm_device *drm);

int vlv_get_cck_clock(struct drm_device *drm,

		      const char *name, u32 reg, int ref_freq);

int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,

int vlv_get_cck_clock_hpll(struct drm_device *drm,

			   const char *name, u32 reg);

bool intel_has_pending_fb_unpin(struct intel_display *display);

void intel_encoder_destroy(struct drm_encoder *encoder);

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −4
Original line number Diff line number Diff line
@@ -1883,12 +1883,11 @@ static void vlv_cmnlane_wa(struct intel_display *display) 


static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	bool ret;



	vlv_punit_get(dev_priv);

	ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;

	vlv_punit_put(dev_priv);

	vlv_punit_get(display->drm);

	ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;

	vlv_punit_put(display->drm);



	return ret;

}