Unverified Commit bd568ce1 authored by Fei Shao's avatar Fei Shao Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8188: Add audio support 



Add following nodes to support audio enablement on MT8188 SoC:
- sound card
- audio controller (AFE)
- audio DSP and its associated mailboxes

Signed-off-by: default avatarFei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20240911143429.850071-8-fshao@chromium.org


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 86bc9aef

arch/arm64/boot/dts/mediatek/mt8188.dtsi

+96 −0
Original line number Diff line number Diff line
@@ -429,6 +429,11 @@ psci { 
		method = "smc";

	};



	sound: sound {

		mediatek,platform = <&afe>;

		status = "disabled";

	};



	thermal_zones: thermal-zones {

		cpu-little0-thermal {

			polling-delay = <1000>;
@@ -1352,6 +1357,97 @@ scp: scp@10500000 { 
			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;

		};



		afe: audio-controller@10b10000 {

			compatible = "mediatek,mt8188-afe";

			reg = <0 0x10b10000 0 0x10000>;

			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;

			assigned-clock-parents =  <&clk26m>;

			clocks = <&clk26m>,

				 <&apmixedsys CLK_APMIXED_APLL1>,

				 <&apmixedsys CLK_APMIXED_APLL2>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV0>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV1>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV2>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV3>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV9>,

				 <&topckgen CLK_TOP_A1SYS_HP>,

				 <&topckgen CLK_TOP_AUD_INTBUS>,

				 <&topckgen CLK_TOP_AUDIO_H>,

				 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,

				 <&topckgen CLK_TOP_DPTX>,

				 <&topckgen CLK_TOP_I2SO1>,

				 <&topckgen CLK_TOP_I2SO2>,

				 <&topckgen CLK_TOP_I2SI1>,

				 <&topckgen CLK_TOP_I2SI2>,

				 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>,

				 <&topckgen CLK_TOP_APLL1_D4>,

				 <&topckgen CLK_TOP_APLL2_D4>,

				 <&topckgen CLK_TOP_APLL12_CK_DIV4>,

				 <&topckgen CLK_TOP_A2SYS>,

				 <&topckgen CLK_TOP_AUD_IEC>;

			clock-names = "clk26m",

				      "apll1",

				      "apll2",

				      "apll12_div0",

				      "apll12_div1",

				      "apll12_div2",

				      "apll12_div3",

				      "apll12_div9",

				      "top_a1sys_hp",

				      "top_aud_intbus",

				      "top_audio_h",

				      "top_audio_local_bus",

				      "top_dptx",

				      "top_i2so1",

				      "top_i2so2",

				      "top_i2si1",

				      "top_i2si2",

				      "adsp_audio_26m",

				      "apll1_d4",

				      "apll2_d4",

				      "apll12_div4",

				      "top_a2sys",

				      "top_aud_iec";

			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;

			resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>;

			reset-names = "audiosys";

			mediatek,infracfg = <&infracfg_ao>;

			mediatek,topckgen = <&topckgen>;

			status = "disabled";

		};



		adsp: adsp@10b80000 {

			compatible = "mediatek,mt8188-dsp";

			reg = <0 0x10b80000 0 0x2000>,

			      <0 0x10d00000 0 0x80000>,

			      <0 0x10b8b000 0 0x100>,

			      <0 0x10b8f000 0 0x1000>;

			reg-names = "cfg", "sram", "sec", "bus";

			assigned-clocks = <&topckgen CLK_TOP_ADSP>;

			clocks = <&topckgen CLK_TOP_ADSP>,

				 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;

			clock-names = "audiodsp", "adsp_bus";

			mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;

			mbox-names = "rx", "tx";

			power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;

			status = "disabled";

		};



		adsp_mailbox0: mailbox@10b86100 {

			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";

			reg = <0 0x10b86100 0 0x1000>;

			interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <0>;

		};



		adsp_mailbox1: mailbox@10b87100 {

			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";

			reg = <0 0x10b87100 0 0x1000>;

			interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <0>;

		};



		adsp_audio26m: clock-controller@10b91100 {

			compatible = "mediatek,mt8188-adsp-audio26m";

			reg = <0 0x10b91100 0 0x100>;