Unverified Commit bd60f94a authored by Clément Le Goffic's avatar Clément Le Goffic Committed by Mark Brown
Browse files

spi: dt-bindings: stm32: update bindings with SPI Rx DMA-MDMA chaining



Add MDMA channel, and new sram property which are mandatory to enable
SPI Rx DMA-MDMA chaining.

Signed-off-by: default avatarClément Le Goffic <clement.legoffic@foss.st.com>
Link: https://patch.msgid.link/20250616-spi-upstream-v1-3-7e8593f3f75d@foss.st.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4956bf44
Loading
Loading
Loading
Loading
+46 −2
Original line number Diff line number Diff line
@@ -18,6 +18,38 @@ maintainers:

allOf:
  - $ref: spi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: st,stm32f4-spi

    then:
      properties:
        st,spi-midi-ns: false
        sram: false
        dmas:
          maxItems: 2
        dma-names:
          items:
            - const: rx
            - const: tx

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp25-spi

    then:
      properties:
        sram: false
        dmas:
          maxItems: 2
        dma-names:
          items:
            - const: rx
            - const: tx

properties:
  compatible:
@@ -41,16 +73,28 @@ properties:

  dmas:
    description: |
      DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
      the STM32 DMA controllers bindings Documentation/devicetree/bindings/dma/stm32/*.yaml.
      DMA specifiers for tx and rx channels. DMA fifo mode must be used. See
      the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml
    minItems: 2
    items:
      - description: rx DMA channel
      - description: tx DMA channel
      - description: rxm2m MDMA channel

  dma-names:
    minItems: 2
    items:
      - const: rx
      - const: tx
      - const: rxm2m

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Phandles to a reserved SRAM region which is used as temporary
      storage memory between DMA and MDMA engines.
      The region should be defined as child node of the AHB SRAM node
      as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml

  access-controllers:
    minItems: 1