Commit bd77b870 authored by Louis-Alexis Eyraud's avatar Louis-Alexis Eyraud Committed by Steven Price
Browse files

drm/panfrost: Commonize Mediatek power domain array definitions 



In the panfrost driver, the platform data of several Mediatek SoC
declares and uses several different power domains arrays according to
GPU core number present in the SoC:
- mediatek_mt8186_pm_domains (2 cores)
- mediatek_mt8183_pm_domains (3 cores)
- mediatek_mt8192_pm_domains (5 cores)

As they all are fixed arrays, starting with the same entries and the
platform data also has a power domains array length field
(num_pm_domains), they can be replaced by a single array, containing
all entries, if the num_pm_domains field of the platform data is also
set to the matching core number.

So, create a generic power domain array (mediatek_pm_domains) and use
it in the mt8183(b), mt8186, mt8188 and mt8192 platform data instead.

Signed-off-by: default avatarLouis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Reviewed-by: default avatarSteven Price <steven.price@arm.com>
Signed-off-by: default avatarSteven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com
parent 6905b0d9

drivers/gpu/drm/panfrost/panfrost_drv.c

+12 −15
Original line number Diff line number Diff line
@@ -866,6 +866,8 @@ static const struct panfrost_compatible amlogic_data = { 
	.vendor_quirk = panfrost_gpu_amlogic_quirk,

};



static const char * const mediatek_pm_domains[] = { "core0", "core1", "core2",

						    "core3", "core4" };

/*

 * The old data with two power supplies for MT8183 is here only to

 * keep retro-compatibility with older devicetrees, as DVFS will
@@ -875,48 +877,43 @@ static const struct panfrost_compatible amlogic_data = { 
 * coupled regulators instead.

 */

static const char * const legacy_supplies[] = { "mali", "sram", NULL };

static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };

static const struct panfrost_compatible mediatek_mt8183_data = {

	.num_supplies = ARRAY_SIZE(legacy_supplies) - 1,

	.supply_names = legacy_supplies,

	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),

	.pm_domain_names = mediatek_mt8183_pm_domains,

	.num_pm_domains = 3,

	.pm_domain_names = mediatek_pm_domains,

};



static const struct panfrost_compatible mediatek_mt8183_b_data = {

	.num_supplies = ARRAY_SIZE(default_supplies) - 1,

	.supply_names = default_supplies,

	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),

	.pm_domain_names = mediatek_mt8183_pm_domains,

	.num_pm_domains = 3,

	.pm_domain_names = mediatek_pm_domains,

	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),

};



static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };

static const struct panfrost_compatible mediatek_mt8186_data = {

	.num_supplies = ARRAY_SIZE(default_supplies) - 1,

	.supply_names = default_supplies,

	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),

	.pm_domain_names = mediatek_mt8186_pm_domains,

	.num_pm_domains = 2,

	.pm_domain_names = mediatek_pm_domains,

	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),

};



/* MT8188 uses the same power domains and power supplies as MT8183 */

static const struct panfrost_compatible mediatek_mt8188_data = {

	.num_supplies = ARRAY_SIZE(default_supplies) - 1,

	.supply_names = default_supplies,

	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),

	.pm_domain_names = mediatek_mt8183_pm_domains,

	.num_pm_domains = 3,

	.pm_domain_names = mediatek_pm_domains,

	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),

	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),

};



static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",

							   "core3", "core4" };

static const struct panfrost_compatible mediatek_mt8192_data = {

	.num_supplies = ARRAY_SIZE(default_supplies) - 1,

	.supply_names = default_supplies,

	.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),

	.pm_domain_names = mediatek_mt8192_pm_domains,

	.num_pm_domains = 5,

	.pm_domain_names = mediatek_pm_domains,

	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),

	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),

};