Commit bd9504af authored by Serge Semin's avatar Serge Semin Committed by Lorenzo Pieralisi
Browse files

dt-bindings: PCI: dwc: Add clocks/resets common properties 

DW PCIe RP/EP reference manuals explicit define all the clocks and reset
requirements in [1] and [2]. Seeing the DW PCIe vendor-specific
DT-bindings have already started assigning random names to the same set of
the clocks and resets lines, let's define a generic names sets and add
them to the DW PCIe common DT-schema.

Note since there are DW PCI-based vendor-specific DT-bindings with the
custom names assigned to the same clocks and resets resources we have no
much choice but to add them to the generic DT-schemas in order to have the
schemas being applicable for such devices. These names are marked as
vendor-specific and should be avoided being used in new bindings in favor
of the generic names.

[1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
Root Port, Version 5.40a, March 2019, p.55 - 78.
[2] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
Endpoint, Version 5.40a, March 2019, p.58 - 81.

Link: https://lore.kernel.org/r/20221113191301.5526-12-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 4cc13eed

Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

+120 −0
Original line number Diff line number Diff line
@@ -58,6 +58,126 @@ properties: 
    minItems: 1

    maxItems: 26



  clocks:

    description:

      DWC PCIe reference manual explicitly defines a set of the clocks required

      to get the controller working correctly. In general all of them can

      be divided into two groups':' application and core clocks. Note the

      platforms may have some of the clock sources unspecified in case if the

      corresponding domains are fed up from a common clock source.

    minItems: 1

    maxItems: 7



  clock-names:

    minItems: 1

    maxItems: 7

    items:

      oneOf:

        - description:

            Data Bus Interface (DBI) clock. Clock signal for the AXI-bus

            interface of the Configuration-Dependent Module, which is

            basically the set of the controller CSRs.

          const: dbi

        - description:

            Application AXI-bus Master interface clock. Basically this is

            a clock for the controller DMA interface (PCI-to-CPU).

          const: mstr

        - description:

            Application AXI-bus Slave interface clock. This is a clock for

            the CPU-to-PCI memory IO interface.

          const: slv

        - description:

            Controller Core-PCS PIPE interface clock. It's normally

            supplied by an external PCS-PHY.

          const: pipe

        - description:

            Controller Primary clock. It's assumed that all controller input

            signals (except resets) are synchronous to this clock.

          const: core

        - description:

            Auxiliary clock for the controller PMC domain. The controller

            partitioning implies having some parts to operate with this

            clock in some power management states.

          const: aux

        - description:

            Generic reference clock. In case if there are several

            interfaces fed up with a common clock source it's advisable to

            define it with this name (for instance pipe, core and aux can

            be connected to a single source of the periodic signal).

          const: ref

        - description:

            Clock for the PHY registers interface. Originally this is

            a PHY-viewport-based interface, but some platform may have

            specifically designed one.

          const: phy_reg

        - description:

            Vendor-specific clock names. Consider using the generic names

            above for new bindings.

          oneOf:

            - description: See native 'dbi' clock for details

              enum: [ pcie, pcie_apb_sys, aclk_dbi ]

            - description: See native 'mstr/slv' clock for details

              enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]

            - description: See native 'pipe' clock for details

              enum: [ pcie_phy, pcie_phy_ref, link ]

            - description: See native 'aux' clock for details

              enum: [ pcie_aux ]

            - description: See native 'ref' clock for details.

              enum: [ gio ]

            - description: See nativs 'phy_reg' clock for details

              enum: [ pcie_apb_phy, pclk ]



  resets:

    description:

      DWC PCIe reference manual explicitly defines a set of the reset

      signals required to be de-asserted to properly activate the controller

      sub-parts. All of these signals can be divided into two sub-groups':'

      application and core resets with respect to the main sub-domains they

      are supposed to reset. Note the platforms may have some of these signals

      unspecified in case if they are automatically handled or aggregated into

      a comprehensive control module.

    minItems: 1

    maxItems: 10



  reset-names:

    minItems: 1

    maxItems: 10

    items:

      oneOf:

        - description: Data Bus Interface (DBI) domain reset

          const: dbi

        - description: AXI-bus Master interface reset

          const: mstr

        - description: AXI-bus Slave interface reset

          const: slv

        - description: Application-dependent interface reset

          const: app

        - description: Controller Non-sticky CSR flags reset

          const: non-sticky

        - description: Controller sticky CSR flags reset

          const: sticky

        - description: PIPE-interface (Core-PCS) logic reset

          const: pipe

        - description:

            Controller primary reset (resets everything except PMC module)

          const: core

        - description: PCS/PHY block reset

          const: phy

        - description: PMC hot reset signal

          const: hot

        - description: Cold reset signal

          const: pwr

        - description:

            Vendor-specific reset names. Consider using the generic names

            above for new bindings.

          oneOf:

            - description: See native 'app' reset for details

              enum: [ apps, gio, apb ]

            - description: See native 'phy' reset for details

              enum: [ pciephy, link ]

            - description: See native 'pwr' reset for details

              enum: [ turnoff ]



  phys:

    description:

      There can be up to the number of possible lanes PHYs specified placed in

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

+6 −0
Original line number Diff line number Diff line
@@ -180,6 +180,12 @@ examples: 
      interrupts = <23>, <24>;

      interrupt-names = "dma0", "dma1";



      clocks = <&sys_clk 12>, <&sys_clk 24>;

      clock-names = "dbi", "ref";



      resets = <&sys_rst 12>, <&sys_rst 24>;

      reset-names = "dbi", "phy";



      phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;

      phy-names = "pcie0", "pcie1", "pcie2", "pcie3";

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

+0 −2
Original line number Diff line number Diff line
@@ -195,8 +195,6 @@ properties: 
      - contains:

          const: msi



  clocks: true



additionalProperties: true



required: