Commit bd98cbbb authored by Dave Jiang's avatar Dave Jiang Committed by Dan Williams
Browse files

ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes 



Update acpi_get_genport_coordinates() to allow retrieval of both access
classes of the 'struct access_coordinate' for a generic target. The update
will allow CXL code to compute access coordinates for both access class.

Cc: Rafael J. Wysocki <rafael@kernel.org>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20240308220055.2172956-5-dave.jiang@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 1745a7b3

drivers/acpi/numa/hmat.c

+6 −2
Original line number Diff line number Diff line
@@ -126,7 +126,8 @@ static struct memory_target *acpi_find_genport_target(u32 uid) 
/**

 * acpi_get_genport_coordinates - Retrieve the access coordinates for a generic port

 * @uid: ACPI unique id

 * @coord: The access coordinates written back out for the generic port

 * @coord: The access coordinates written back out for the generic port.

 *	   Expect 2 levels array.

 *

 * Return: 0 on success. Errno on failure.

 *
@@ -142,7 +143,10 @@ int acpi_get_genport_coordinates(u32 uid, 
	if (!target)

		return -ENOENT;



	*coord = target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL];

	coord[ACCESS_COORDINATE_LOCAL] =

		target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL];

	coord[ACCESS_COORDINATE_CPU] =

		target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_CPU];



	return 0;

}

drivers/cxl/acpi.c

+5 −3
Original line number Diff line number Diff line
@@ -530,13 +530,15 @@ static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport) 
	if (kstrtou32(acpi_device_uid(hb), 0, &uid))

		return -EINVAL;



	rc = acpi_get_genport_coordinates(uid, &dport->hb_coord);

	rc = acpi_get_genport_coordinates(uid, dport->hb_coord);

	if (rc < 0)

		return rc;



	/* Adjust back to picoseconds from nanoseconds */

	dport->hb_coord.read_latency *= 1000;

	dport->hb_coord.write_latency *= 1000;

	for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {

		dport->hb_coord[i].read_latency *= 1000;

		dport->hb_coord[i].write_latency *= 1000;

	}



	return 0;

}

drivers/cxl/core/port.c

+1 −1
Original line number Diff line number Diff line
@@ -2152,7 +2152,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 
	}



	/* Augment with the generic port (host bridge) perf data */

	combine_coordinates(&c, &dport->hb_coord);

	combine_coordinates(&c, &dport->hb_coord[ACCESS_COORDINATE_LOCAL]);



	/* Get the calculated PCI paths bandwidth */

	pdev = to_pci_dev(port->uport_dev->parent);

drivers/cxl/cxl.h

+1 −1
Original line number Diff line number Diff line
@@ -671,7 +671,7 @@ struct cxl_dport { 
	struct cxl_port *port;

	struct cxl_regs regs;

	struct access_coordinate sw_coord;

	struct access_coordinate hb_coord;

	struct access_coordinate hb_coord[ACCESS_COORDINATE_MAX];

	long link_latency;

};