Commit bdbb6a14 authored Aug 14, 2025 by Clay King Committed by Alex Deucher Aug 27, 2025

drm/amd/display: Array offset used before range check



Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent f382e2d0

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -280,7 +280,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_p
		j = 0;
		/* create the final dcfclk and uclk table */
		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
		dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
		dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
		} else {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -285,7 +285,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_p
		j = 0;
		/* create the final dcfclk and uclk table */
		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
		dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
		dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
		} else {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3229,7 +3229,7 @@ void dcn32_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_pa
		j = 0;
		// create the final dcfclk and uclk table
		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
		dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
		dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
		} else {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -779,7 +779,7 @@ void dcn321_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_p
		j = 0;
		// create the final dcfclk and uclk table
		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
		dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
		dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
		} else {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2192,7 +2192,7 @@ void dcn30_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_params
		j = 0;
		// create the final dcfclk and uclk table
		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
		if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
		dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
		dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
		} else {