Loading include/asm-mips/mach-db1x00/db1200.h +3 −0 Original line number Diff line number Diff line Loading @@ -220,5 +220,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BOARD_PC1_INT DB1200_PC1_INT #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) /* Nand chip select */ #define NAND_CS 1 #endif /* __ASM_DB1200_H */ include/asm-mips/mach-db1x00/db1x00.h +6 −0 Original line number Diff line number Diff line Loading @@ -200,6 +200,12 @@ typedef volatile struct ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) #define NAND_CS 1 /* should be done by yamon */ #define NAND_STCFG 0x00400005 /* 8-bit NAND */ #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_DB1X00_H */ include/asm-mips/mach-pb1x00/pb1200.h +3 −0 Original line number Diff line number Diff line Loading @@ -248,5 +248,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BOARD_PC1_INT PB1200_PC1_INT #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) /* Nand chip select */ #define NAND_CS 1 #endif /* __ASM_PB1200_H */ include/asm-mips/mach-pb1x00/pb1550.h +7 −0 Original line number Diff line number Diff line Loading @@ -166,4 +166,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) #define NAND_CS 1 /* should be done by yamon */ #define NAND_STCFG 0x00400005 /* 8-bit NAND */ #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_PB1550_H */ Loading
include/asm-mips/mach-db1x00/db1200.h +3 −0 Original line number Diff line number Diff line Loading @@ -220,5 +220,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BOARD_PC1_INT DB1200_PC1_INT #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) /* Nand chip select */ #define NAND_CS 1 #endif /* __ASM_DB1200_H */
include/asm-mips/mach-db1x00/db1x00.h +6 −0 Original line number Diff line number Diff line Loading @@ -200,6 +200,12 @@ typedef volatile struct ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) #define NAND_CS 1 /* should be done by yamon */ #define NAND_STCFG 0x00400005 /* 8-bit NAND */ #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_DB1X00_H */
include/asm-mips/mach-pb1x00/pb1200.h +3 −0 Original line number Diff line number Diff line Loading @@ -248,5 +248,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BOARD_PC1_INT PB1200_PC1_INT #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) /* Nand chip select */ #define NAND_CS 1 #endif /* __ASM_PB1200_H */
include/asm-mips/mach-pb1x00/pb1550.h +7 −0 Original line number Diff line number Diff line Loading @@ -166,4 +166,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) #define NAND_CS 1 /* should be done by yamon */ #define NAND_STCFG 0x00400005 /* 8-bit NAND */ #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_PB1550_H */