Commit be208c0c authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags 



Update the GDSC wait_val fields as per the default hardware values as
otherwise they would lead to GDSC FSM state to be stuck and causing
failures to power on/off. Also add the GDSC flags as applicable and
add support to control PCIE GDSC's using collapse vote registers.

Fixes: 08c51ceb ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-2-adcc756a23df@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent d3b33848

drivers/clk/qcom/gcc-sa8775p.c

+40 −0
Original line number Diff line number Diff line
@@ -4203,74 +4203,114 @@ static struct clk_branch gcc_video_axi1_clk = { 


static struct gdsc pcie_0_gdsc = {

	.gdscr = 0xa9004,

	.collapse_ctrl = 0x4b104,

	.collapse_mask = BIT(0),

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "pcie_0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc pcie_1_gdsc = {

	.gdscr = 0x77004,

	.collapse_ctrl = 0x4b104,

	.collapse_mask = BIT(1),

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "pcie_1_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc ufs_card_gdsc = {

	.gdscr = 0x81004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ufs_card_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc ufs_phy_gdsc = {

	.gdscr = 0x83004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ufs_phy_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc usb20_prim_gdsc = {

	.gdscr = 0x1c004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "usb20_prim_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc usb30_prim_gdsc = {

	.gdscr = 0x1b004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "usb30_prim_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc usb30_sec_gdsc = {

	.gdscr = 0x2f004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "usb30_sec_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc emac0_gdsc = {

	.gdscr = 0xb6004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "emac0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct gdsc emac1_gdsc = {

	.gdscr = 0xb4004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "emac1_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

};



static struct clk_regmap *gcc_sa8775p_clocks[] = {