Commit be2fce78 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dmc: Also disable the flip queue event on TGL main DMC 



Unlike later platforms TGL has its flip queue event (CLK_MSEC) on
the main DMC (as opposed to the pipe DMC). Currently we're doing
a second pass to disable that, but let's just follow the same
approach as the later platforms and never even enable the event
in the first place.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211213750.27109-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent 648d7be8

drivers/gpu/drm/i915/display/intel_dmc.c

+5 −78
Original line number Diff line number Diff line
@@ -335,77 +335,6 @@ static void disable_event_handler(struct drm_i915_private *i915, 
	intel_de_write(i915, htp_reg, 0);

}



static void

disable_flip_queue_event(struct drm_i915_private *i915,

			 i915_reg_t ctl_reg, i915_reg_t htp_reg)

{

	u32 event_ctl;

	u32 event_htp;



	event_ctl = intel_de_read(i915, ctl_reg);

	event_htp = intel_de_read(i915, htp_reg);

	if (event_ctl != (DMC_EVT_CTL_ENABLE |

			  DMC_EVT_CTL_RECURRING |

			  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

					 DMC_EVT_CTL_TYPE_EDGE_0_1) |

			  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

					 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||

	    !event_htp) {

		drm_dbg_kms(&i915->drm,

			    "Unexpected DMC event configuration (control %08x htp %08x)\n",

			    event_ctl, event_htp);

		return;

	}



	disable_event_handler(i915, ctl_reg, htp_reg);

}



static bool

get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id,

			  i915_reg_t *ctl_reg, i915_reg_t *htp_reg)

{

	if (dmc_id == DMC_FW_MAIN) {

		if (DISPLAY_VER(i915) == 12) {

			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);

			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);



			return true;

		}

	} else if (dmc_id >= DMC_FW_PIPEA && dmc_id <= DMC_FW_PIPED) {

		if (IS_DG2(i915)) {

			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);

			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);



			return true;

		}

	}



	return false;

}



static void

disable_all_flip_queue_events(struct drm_i915_private *i915)

{

	enum intel_dmc_id dmc_id;



	/* TODO: check if the following applies to all D13+ platforms. */

	if (!IS_TIGERLAKE(i915))

		return;



	for_each_dmc_id(dmc_id) {

		i915_reg_t ctl_reg;

		i915_reg_t htp_reg;



		if (!has_dmc_id_fw(i915, dmc_id))

			continue;



		if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg))

			continue;



		disable_flip_queue_event(i915, ctl_reg, htp_reg);

	}

}



static void disable_all_event_handlers(struct drm_i915_private *i915)

{

	enum intel_dmc_id dmc_id;
@@ -514,6 +443,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915, 
	if (dmc_id != DMC_FW_MAIN)

		return true;



	/* also disable the flip queue event on the main DMC on TGL */

	if (IS_TIGERLAKE(i915) &&

	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)

		return true;



	return false;

}
@@ -579,13 +513,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915) 


	gen9_set_dc_state_debugmask(i915);



	/*

	 * Flip queue events need to be disabled before enabling DC5/6.

	 * i915 doesn't use the flip queue feature, so disable it already

	 * here.

	 */

	disable_all_flip_queue_events(i915);



	pipedmc_clock_gating_wa(i915, false);

}