Commit be4463fa authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Peter Zijlstra
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sched/mmcid: Cacheline align MM CID storage 



Both the per CPU storage and the data in mm_struct are heavily used in
context switch. As they can end up next to other frequently modified data,
they are subject to false sharing.

Make them cache line aligned.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://patch.msgid.link/20251119172549.194111661@linutronix.de
parent 8cea569c

include/linux/rseq_types.h

+2 −2
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ struct sched_mm_cid { 
 */

struct mm_cid_pcpu {

	unsigned int	cid;

};

}____cacheline_aligned_in_smp;



/**

 * struct mm_mm_cid - Storage for per MM CID data
@@ -126,7 +126,7 @@ struct mm_mm_cid { 
	struct mm_cid_pcpu	__percpu *pcpu;

	unsigned int		nr_cpus_allowed;

	raw_spinlock_t		lock;

};

}____cacheline_aligned_in_smp;

#else /* CONFIG_SCHED_MM_CID */

struct mm_mm_cid { };

struct sched_mm_cid { };