Commit be4e3509 authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: DML21 Reintegration For Various Fixes 



Reintegrate latest DML21 code.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bb4090cd

drivers/gpu/drm/amd/display/dc/dml2/Makefile

+6 −9
Original line number Diff line number Diff line
@@ -73,9 +73,8 @@ AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2/,$(DML2)) 


AMD_DISPLAY_FILES += $(AMD_DAL_DML2)



CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml_top.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml_top_mcache.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags)
@@ -94,9 +93,8 @@ CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_ccflags) 
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/inc/dml2_debug.o := $(dml2_ccflags)



CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml_top.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml_top_mcache.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags)
@@ -113,9 +111,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_r 
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/inc/dml2_debug.o := $(dml2_rcflags)



DML21 := src/dml2_top/dml_top.o

DML21 += src/dml2_top/dml_top_mcache.o

DML21 += src/dml2_top/dml2_top_optimization.o

DML21 := src/dml2_top/dml2_top_interfaces.o

DML21 += src/dml2_top/dml2_top_soc15.o

DML21 += src/inc/dml2_debug.o

DML21 += src/dml2_core/dml2_core_dcn4.o

DML21 += src/dml2_core/dml2_core_factory.o

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c

+3 −3
Original line number Diff line number Diff line
@@ -8318,7 +8318,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc 
	if (clk_cfg->dcfclk_option != dml_use_override_freq)

		locals->Dcfclk = mode_lib->ms.DCFCLK;

	else

		locals->Dcfclk = clk_cfg->dcfclk_freq_mhz;

		locals->Dcfclk = clk_cfg->dcfclk_mhz;









#ifdef __DML_VBA_DEBUG__









	dml_print_dml_policy(&mode_lib->ms.policy);








@@ -8371,7 +8371,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc







	if (clk_cfg->dispclk_option == dml_use_required_freq)









		locals->Dispclk = locals->Dispclk_calculated;









	else if (clk_cfg->dispclk_option == dml_use_override_freq)









		locals->Dispclk = clk_cfg->dispclk_freq_mhz;









		locals->Dispclk = clk_cfg->dispclk_mhz;









	else









		locals->Dispclk = mode_lib->ms.state.dispclk_mhz;









#ifdef __DML_VBA_DEBUG__








@@ -8412,7 +8412,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc







		if (clk_cfg->dppclk_option[k] == dml_use_required_freq)









			locals->Dppclk[k] = locals->Dppclk_calculated[k];









		else if (clk_cfg->dppclk_option[k] == dml_use_override_freq)









			locals->Dppclk[k] = clk_cfg->dppclk_freq_mhz[k];









			locals->Dppclk[k] = clk_cfg->dppclk_mhz[k];









		else









			locals->Dppclk[k] = mode_lib->ms.state.dppclk_mhz;









#ifdef __DML_VBA_DEBUG__
































drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h



+80
−23






























Original line number
Diff line number
Diff line







@@ -28,6 +28,7 @@







#define __DISPLAY_MODE_CORE_STRUCT_H__



















#include "display_mode_lib_defines.h"









#include "dml_top_display_cfg_types.h"



















enum dml_project_id {









	dml_project_invalid = 0,








@@ -49,7 +50,9 @@ enum dml_use_mall_for_pstate_change_mode {







	dml_use_mall_pstate_change_disable = 0,









	dml_use_mall_pstate_change_full_frame = 1,









	dml_use_mall_pstate_change_sub_viewport = 2,









	dml_use_mall_pstate_change_phantom_pipe = 3









	dml_use_mall_pstate_change_phantom_pipe = 3,









	dml_use_mall_pstate_change_phantom_pipe_no_data_return = 4,









	dml_use_mall_pstate_change_imall = 5









};









enum dml_use_mall_for_static_screen_mode {









	dml_use_mall_static_screen_disable = 0,








@@ -171,7 +174,11 @@ enum dml_swizzle_mode {







	dml_sw_256kb_z_x = 28,









	dml_sw_256kb_s_x = 29,









	dml_sw_256kb_d_x = 30,









	dml_sw_256kb_r_x = 31









	dml_sw_256kb_r_x = 31,









	dml_sw_256b_2d = 32,









	dml_sw_4kb_2d = 33,









	dml_sw_64kb_2d = 34,









	dml_sw_256kb_2d = 35









};









enum dml_lb_depth {









	dml_lb_6 = 0,








@@ -223,24 +230,28 @@ enum dml_mpc_use_policy {







	dml_mpc_disabled = 0,









	dml_mpc_as_possible = 1,









	dml_mpc_as_needed_for_voltage = 2,









	dml_mpc_as_needed_for_pstate_and_voltage = 3









	dml_mpc_as_needed_for_pstate_and_voltage = 3,









	dml_mpc_as_needed = 4,









	dml_mpc_2to1 = 5









};









enum dml_odm_use_policy {









	dml_odm_use_policy_bypass = 0,









	dml_odm_use_policy_combine_as_needed = 1,









	dml_odm_use_policy_combine_2to1 = 2,









	dml_odm_use_policy_combine_4to1 = 3,









	dml_odm_use_policy_split_1to2 = 4,









	dml_odm_use_policy_mso_1to2 = 5,









	dml_odm_use_policy_mso_1to4 = 6









	dml_odm_use_policy_combine_3to1 = 3,









	dml_odm_use_policy_combine_4to1 = 4,









	dml_odm_use_policy_split_1to2 = 5,









	dml_odm_use_policy_mso_1to2 = 6,









	dml_odm_use_policy_mso_1to4 = 7









};









enum dml_odm_mode {









	dml_odm_mode_bypass = 0,









	dml_odm_mode_combine_2to1 = 1,









	dml_odm_mode_combine_4to1 = 2,









	dml_odm_mode_split_1to2 = 3,









	dml_odm_mode_mso_1to2 = 4,









	dml_odm_mode_mso_1to4 = 5









	dml_odm_mode_combine_3to1 = 2,









	dml_odm_mode_combine_4to1 = 3,









	dml_odm_mode_split_1to2 = 4,









	dml_odm_mode_mso_1to2 = 5,









	dml_odm_mode_mso_1to4 = 6









};









enum dml_writeback_configuration {









	dml_whole_buffer_for_single_stream_no_interleave = 0,








@@ -289,6 +300,17 @@ struct soc_state_bounding_box_st {







	dml_float_t fclk_change_latency_us;









	dml_float_t usr_retraining_latency_us;









	dml_bool_t use_ideal_dram_bw_strobe;









	dml_float_t g6_temp_read_blackout_us;



















	struct {









		dml_uint_t urgent_ramp_uclk_cycles;









		dml_uint_t trip_to_memory_uclk_cycles;









		dml_uint_t meta_trip_to_memory_uclk_cycles;









		dml_uint_t maximum_latency_when_urgent_uclk_cycles;









		dml_uint_t average_latency_when_urgent_uclk_cycles;









		dml_uint_t maximum_latency_when_non_urgent_uclk_cycles;









		dml_uint_t average_latency_when_non_urgent_uclk_cycles;









	}  dml_dcn401_uclk_dpm_dependent_soc_qos_params;









};



















struct soc_bounding_box_st {








@@ -297,7 +319,7 @@ struct soc_bounding_box_st {







	dml_float_t pcierefclk_mhz;









	dml_float_t refclk_mhz;









	dml_float_t amclk_mhz;









	dml_float_t max_outstanding_reqs;









	dml_uint_t max_outstanding_reqs;









	dml_float_t pct_ideal_sdp_bw_after_urgent;









	dml_float_t pct_ideal_fabric_bw_after_urgent;









	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only;








@@ -308,6 +330,16 @@ struct soc_bounding_box_st {







	dml_float_t max_avg_fabric_bw_use_normal_percent;









	dml_float_t max_avg_dram_bw_use_normal_percent;









	dml_float_t max_avg_dram_bw_use_normal_strobe_percent;



















	dml_float_t svp_prefetch_pct_ideal_sdp_bw_after_urgent;









	dml_float_t svp_prefetch_pct_ideal_fabric_bw_after_urgent;









	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only;









	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_and_vm;









	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only;









	dml_float_t svp_prefetch_max_avg_sdp_bw_use_normal_percent;









	dml_float_t svp_prefetch_max_avg_fabric_bw_use_normal_percent;









	dml_float_t svp_prefetch_max_avg_dram_bw_use_normal_percent;



















	dml_uint_t round_trip_ping_latency_dcfclk_cycles;









	dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes;









	dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;








@@ -324,6 +356,26 @@ struct soc_bounding_box_st {







	dml_uint_t mall_allocated_for_dcn_mbytes;









	dml_float_t dispclk_dppclk_vco_speed_mhz;









	dml_bool_t do_urgent_latency_adjustment;



















	dml_uint_t mem_word_bytes;









	dml_uint_t num_dcc_mcaches;









	dml_uint_t mcache_size_bytes;









	dml_uint_t mcache_line_size_bytes;



















	struct {









		dml_bool_t UseNewDCN401SOCParameters;









		dml_uint_t df_qos_response_time_fclk_cycles;









		dml_uint_t max_round_trip_to_furthest_cs_fclk_cycles;









		dml_uint_t mall_overhead_fclk_cycles;









		dml_uint_t meta_trip_adder_fclk_cycles;









		dml_uint_t average_transport_distance_fclk_cycles;









		dml_float_t umc_urgent_ramp_latency_margin;









		dml_float_t umc_max_latency_margin;









		dml_float_t umc_average_latency_margin;









		dml_float_t fabric_max_transport_latency_margin;









		dml_float_t fabric_average_transport_latency_margin;









	}  dml_dcn401_soc_qos_params;



















};



















struct ip_params_st {








@@ -515,6 +567,10 @@ struct dml_plane_cfg_st {







	dml_uint_t CursorWidth[__DML_NUM_PLANES__];









	dml_uint_t CursorBPP[__DML_NUM_PLANES__];



















	dml_bool_t setup_for_tdlut[__DML_NUM_PLANES__];









	enum dml2_tdlut_addressing_mode tdlut_addressing_mode[__DML_NUM_PLANES__];









	enum dml2_tdlut_width_mode tdlut_width_mode[__DML_NUM_PLANES__];



















	enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__];









	enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__];


















@@ -604,6 +660,17 @@ struct dml_hw_resource_st {







	dml_float_t DLGRefClkFreqMHz; /// <brief DLG Global Reference timer









};



















/// @brief To control the clk usage for model programming









struct dml_clk_cfg_st {









	enum dml_clk_cfg_policy dcfclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq









	enum dml_clk_cfg_policy dispclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq









	enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];



















	dml_float_t dcfclk_mhz;









	dml_float_t dispclk_mhz;









	dml_float_t dppclk_mhz[__DML_NUM_PLANES__];









}; // dml_clk_cfg_st



















/// @brief DML display configuration.









///        Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin









struct dml_display_cfg_st {








@@ -616,19 +683,9 @@ struct dml_display_cfg_st {







	unsigned int num_timings;



















	struct dml_hw_resource_st hw; //< brief for mode programming









	struct dml_clk_cfg_st clk_overrides;   //< brief for mode programming clk override









}; // dml_display_cfg_st



















/// @brief To control the clk usage for model programming









struct dml_clk_cfg_st {









	enum dml_clk_cfg_policy dcfclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq









	enum dml_clk_cfg_policy dispclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq









	enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];



















	dml_float_t dcfclk_freq_mhz;









	dml_float_t dispclk_freq_mhz;









	dml_float_t dppclk_freq_mhz[__DML_NUM_PLANES__];









}; // dml_clk_cfg_st



















/// @brief DML mode evaluation and programming policy









/// Those knobs that affect mode support and mode programming









struct dml_mode_eval_policy_st {
































drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c



+3
−3






























Original line number
Diff line number
Diff line







@@ -690,12 +690,12 @@ __DML_DLL_EXPORT__ void dml_print_clk_cfg(const struct dml_clk_cfg_st *clk_cfg)







	dml_print("DML: clk_cfg: dcfclk_option = %d\n", clk_cfg->dcfclk_option);









	dml_print("DML: clk_cfg: dispclk_option = %d\n", clk_cfg->dispclk_option);



















	dml_print("DML: clk_cfg: dcfclk_freq_mhz = %f\n", clk_cfg->dcfclk_freq_mhz);









	dml_print("DML: clk_cfg: dispclk_freq_mhz = %f\n", clk_cfg->dispclk_freq_mhz);









	dml_print("DML: clk_cfg: dcfclk_mhz = %f\n", clk_cfg->dcfclk_mhz);









	dml_print("DML: clk_cfg: dispclk_mhz = %f\n", clk_cfg->dispclk_mhz);



















	for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) {









		dml_print("DML: clk_cfg: i=%d, dppclk_option = %d\n", i, clk_cfg->dppclk_option[i]);









		dml_print("DML: clk_cfg: i=%d, dppclk_freq_mhz = %f\n", i, clk_cfg->dppclk_freq_mhz[i]);









		dml_print("DML: clk_cfg: i=%d, dppclk_mhz = %f\n", i, clk_cfg->dppclk_mhz[i]);









	}









}










































drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c



+7
−7






























Original line number
Diff line number
Diff line







@@ -1226,22 +1226,22 @@ void dml21_set_dc_p_state_type(







		bool sub_vp_enabled)









{









	switch (stream_programming->uclk_pstate_method) {









	case dml2_uclk_pstate_support_method_vactive:









	case dml2_uclk_pstate_support_method_fw_vactive_drr:









	case dml2_pstate_method_vactive:









	case dml2_pstate_method_fw_vactive_drr:









		pipe_ctx->p_state_type = P_STATE_V_ACTIVE;









		break;









	case dml2_uclk_pstate_support_method_vblank:









	case dml2_uclk_pstate_support_method_fw_vblank_drr:









	case dml2_pstate_method_vblank:









	case dml2_pstate_method_fw_vblank_drr:









		if (sub_vp_enabled)









			pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;









		else









			pipe_ctx->p_state_type = P_STATE_V_BLANK;









		break;









	case dml2_uclk_pstate_support_method_fw_subvp_phantom:









	case dml2_uclk_pstate_support_method_fw_subvp_phantom_drr:









	case dml2_pstate_method_fw_svp:









	case dml2_pstate_method_fw_svp_drr:









		pipe_ctx->p_state_type = P_STATE_SUB_VP;









		break;









	case dml2_uclk_pstate_support_method_fw_drr:









	case dml2_pstate_method_fw_drr:









		if (sub_vp_enabled)









			pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;









		else