Commit be548645 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm fixes from Paolo Bonzini:
 "The largest part here is for KVM/PPC, where a NULL pointer dereference
  was introduced in the 6.13 merge window and is now fixed.

  There's some "holiday-induced lateness", as the s390 submaintainer put
  it, but otherwise things looks fine.

  s390:

   - fix a latent bug when the kernel is compiled in debug mode

   - two small UCONTROL fixes and their selftests

  arm64:

   - always check page state in hyp_ack_unshare()

   - align set_id_regs selftest with the fact that ASIDBITS field is RO

   - various vPMU fixes for bugs that only affect nested virt

  PPC e500:

   - Fix a mostly impossible (but just wrong) case where IRQs were never
     re-enabled

   - Observe host permissions instead of mapping readonly host pages as
     guest-writable. This fixes a NULL-pointer dereference in 6.13

   - Replace brittle VMA-based attempts at building huge shadow TLB
     entries with PTE lookups"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: e500: perform hugepage check after looking up the PFN
  KVM: e500: map readonly host pages for read
  KVM: e500: track host-writability of pages
  KVM: e500: use shadow TLB entry as witness for writability
  KVM: e500: always restore irqs
  KVM: s390: selftests: Add has device attr check to uc_attr_mem_limit selftest
  KVM: s390: selftests: Add ucontrol gis routing test
  KVM: s390: Reject KVM_SET_GSI_ROUTING on ucontrol VMs
  KVM: s390: selftests: Add ucontrol flic attr selftests
  KVM: s390: Reject setting flic pfault attributes on ucontrol VMs
  KVM: s390: vsie: fix virtual/physical address in unpin_scb()
  KVM: arm64: Only apply PMCR_EL0.P to the guest range of counters
  KVM: arm64: nv: Reload PMU events upon MDCR_EL2.HPME change
  KVM: arm64: Use KVM_REQ_RELOAD_PMU to handle PMCR_EL0.E change
  KVM: arm64: Add unified helper for reprogramming counters by mask
  KVM: arm64: Always check the state from hyp_ack_unshare()
  KVM: arm64: Fix set_id_regs selftest for ASIDBITS becoming unwritable
parents a603abe3 a5546c2f

Documentation/virt/kvm/api.rst

+3 −0
Original line number Diff line number Diff line
@@ -1914,6 +1914,9 @@ No flags are specified so far, the corresponding field must be set to zero. 
  #define KVM_IRQ_ROUTING_HV_SINT 4

  #define KVM_IRQ_ROUTING_XEN_EVTCHN 5



On s390, adding a KVM_IRQ_ROUTING_S390_ADAPTER is rejected on ucontrol VMs with

error -EINVAL.



flags:



- KVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry

Documentation/virt/kvm/devices/s390_flic.rst

+4 −0
Original line number Diff line number Diff line
@@ -58,11 +58,15 @@ Groups: 
    Enables async page faults for the guest. So in case of a major page fault

    the host is allowed to handle this async and continues the guest.



    -EINVAL is returned when called on the FLIC of a ucontrol VM.



  KVM_DEV_FLIC_APF_DISABLE_WAIT

    Disables async page faults for the guest and waits until already pending

    async page faults are done. This is necessary to trigger a completion interrupt

    for every init interrupt before migrating the interrupt list.



    -EINVAL is returned when called on the FLIC of a ucontrol VM.



  KVM_DEV_FLIC_ADAPTER_REGISTER

    Register an I/O adapter interrupt source. Takes a kvm_s390_io_adapter

    describing the adapter to register::

arch/arm64/kvm/hyp/nvhe/mem_protect.c

+0 −3
Original line number Diff line number Diff line
@@ -783,9 +783,6 @@ static int hyp_ack_unshare(u64 addr, const struct pkvm_mem_transition *tx) 
	if (tx->initiator.id == PKVM_ID_HOST && hyp_page_count((void *)addr))

		return -EBUSY;



	if (__hyp_ack_skip_pgtable_check(tx))

		return 0;



	return __hyp_check_page_state_range(addr, size,

					    PKVM_PAGE_SHARED_BORROWED);

}

arch/arm64/kvm/pmu-emul.c

+35 −54
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ static DEFINE_MUTEX(arm_pmus_lock); 


static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc);

static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc);

static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc);



static struct kvm_vcpu *kvm_pmc_to_vcpu(const struct kvm_pmc *pmc)

{
@@ -327,48 +328,25 @@ u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) 
		return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);

}



/**

 * kvm_pmu_enable_counter_mask - enable selected PMU counters

 * @vcpu: The vcpu pointer

 * @val: the value guest writes to PMCNTENSET register

 *

 * Call perf_event_enable to start counting the perf event

 */

void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)

static void kvm_pmc_enable_perf_event(struct kvm_pmc *pmc)

{

	int i;

	if (!kvm_vcpu_has_pmu(vcpu))

		return;



	if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val)

		return;



	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {

		struct kvm_pmc *pmc;



		if (!(val & BIT(i)))

			continue;



		pmc = kvm_vcpu_idx_to_pmc(vcpu, i);



	if (!pmc->perf_event) {

		kvm_pmu_create_perf_event(pmc);

		} else {

		return;

	}



	perf_event_enable(pmc->perf_event);

	if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)

		kvm_debug("fail to enable perf event\n");

}

	}



static void kvm_pmc_disable_perf_event(struct kvm_pmc *pmc)

{

	if (pmc->perf_event)

		perf_event_disable(pmc->perf_event);

}



/**

 * kvm_pmu_disable_counter_mask - disable selected PMU counters

 * @vcpu: The vcpu pointer

 * @val: the value guest writes to PMCNTENCLR register

 *

 * Call perf_event_disable to stop counting the perf event

 */

void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)

void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val)

{

	int i;
@@ -376,16 +354,18 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) 
		return;



	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {

		struct kvm_pmc *pmc;

		struct kvm_pmc *pmc = kvm_vcpu_idx_to_pmc(vcpu, i);



		if (!(val & BIT(i)))

			continue;



		pmc = kvm_vcpu_idx_to_pmc(vcpu, i);



		if (pmc->perf_event)

			perf_event_disable(pmc->perf_event);

		if (kvm_pmu_counter_is_enabled(pmc))

			kvm_pmc_enable_perf_event(pmc);

		else

			kvm_pmc_disable_perf_event(pmc);

	}



	kvm_vcpu_pmu_restore_guest(vcpu);

}



/*
@@ -626,27 +606,28 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) 
	if (!kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5))

		val &= ~ARMV8_PMU_PMCR_LP;



	/* Request a reload of the PMU to enable/disable affected counters */

	if ((__vcpu_sys_reg(vcpu, PMCR_EL0) ^ val) & ARMV8_PMU_PMCR_E)

		kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);



	/* The reset bits don't indicate any state, and shouldn't be saved. */

	__vcpu_sys_reg(vcpu, PMCR_EL0) = val & ~(ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_P);



	if (val & ARMV8_PMU_PMCR_E) {

		kvm_pmu_enable_counter_mask(vcpu,

		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));

	} else {

		kvm_pmu_disable_counter_mask(vcpu,

		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));

	}



	if (val & ARMV8_PMU_PMCR_C)

		kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);



	if (val & ARMV8_PMU_PMCR_P) {

		unsigned long mask = kvm_pmu_accessible_counter_mask(vcpu);

		mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);

		/*

		 * Unlike other PMU sysregs, the controls in PMCR_EL0 always apply

		 * to the 'guest' range of counters and never the 'hyp' range.

		 */

		unsigned long mask = kvm_pmu_implemented_counter_mask(vcpu) &

				     ~kvm_pmu_hyp_counter_mask(vcpu) &

				     ~BIT(ARMV8_PMU_CYCLE_IDX);



		for_each_set_bit(i, &mask, 32)

			kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, i), 0, true);

	}

	kvm_vcpu_pmu_restore_guest(vcpu);

}



static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc)
@@ -910,11 +891,11 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) 
{

	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);



	kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));



	__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;

	__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;

	__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;



	kvm_pmu_reprogram_counter_mask(vcpu, mask);

}



int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)

arch/arm64/kvm/sys_regs.c

+25 −7
Original line number Diff line number Diff line
@@ -1208,16 +1208,14 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	mask = kvm_pmu_accessible_counter_mask(vcpu);

	if (p->is_write) {

		val = p->regval & mask;

		if (r->Op2 & 0x1) {

		if (r->Op2 & 0x1)

			/* accessing PMCNTENSET_EL0 */

			__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;

			kvm_pmu_enable_counter_mask(vcpu, val);

			kvm_vcpu_pmu_restore_guest(vcpu);

		} else {

		else

			/* accessing PMCNTENCLR_EL0 */

			__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;

			kvm_pmu_disable_counter_mask(vcpu, val);

		}



		kvm_pmu_reprogram_counter_mask(vcpu, val);

	} else {

		p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);

	}
@@ -2450,6 +2448,26 @@ static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 
	return __el2_visibility(vcpu, rd, s1pie_visibility);

}



static bool access_mdcr(struct kvm_vcpu *vcpu,

			struct sys_reg_params *p,

			const struct sys_reg_desc *r)

{

	u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2);



	if (!access_rw(vcpu, p, r))

		return false;



	/*

	 * Request a reload of the PMU to enable/disable the counters affected

	 * by HPME.

	 */

	if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME)

		kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);



	return true;

}





/*

 * Architected system registers.

 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -2983,7 +3001,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),

	EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),

	EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),

	EL2_REG(MDCR_EL2, access_rw, reset_val, 0),

	EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0),

	EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),

	EL2_REG_VNCR(HSTR_EL2, reset_val, 0),

	EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),