Commit be6692b9 authored by Qianggui Song's avatar Qianggui Song Committed by Marc Zyngier
Browse files

irqchip/meson-gpio: add select trigger type callback 



Due to some chips may use different registers and offset, provide
a set trigger type call back and add one for old controller.

Signed-off-by: default avatarQianggui Song <qianggui.song@amlogic.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220225055207.1048-4-qianggui.song@amlogic.com
parent cc311074

drivers/irqchip/irq-meson-gpio.c

+13 −7
Original line number Diff line number Diff line
@@ -51,11 +51,15 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 
				      unsigned int channel,

				      unsigned long hwirq);

static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);

static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,

				    unsigned int type, u32 *channel_hwirq);



struct irq_ctl_ops {

	void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,

				 unsigned int channel, unsigned long hwirq);

	void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);

	int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl,

				 unsigned int type, u32 *channel_hwirq);

};



struct meson_gpio_irq_params {
@@ -69,16 +73,18 @@ struct meson_gpio_irq_params { 
	struct irq_ctl_ops ops;

};



#define INIT_MESON_COMMON(irqs, init, sel)			\

#define INIT_MESON_COMMON(irqs, init, sel, type)		\

	.nr_hwirq = irqs,					\

	.ops = {						\

		.gpio_irq_init = init,				\

		.gpio_irq_sel_pin = sel,			\

		.gpio_irq_set_type = type,			\

	},



#define INIT_MESON8_COMMON_DATA(irqs)				\

	INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy,	\

			  meson8_gpio_irq_sel_pin)		\

			  meson8_gpio_irq_sel_pin,		\

			  meson8_gpio_irq_set_type)		\

	.edge_single_offset = 0,				\

	.pol_low_offset = 16,					\

	.pin_sel_mask = 0xff,					\
@@ -86,7 +92,8 @@ struct meson_gpio_irq_params { 


#define INIT_MESON_A1_COMMON_DATA(irqs)				\

	INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,		\

			  meson_a1_gpio_irq_sel_pin)		\

			  meson_a1_gpio_irq_sel_pin,		\

			  meson8_gpio_irq_set_type)		\

	.support_edge_both = true,				\

	.edge_both_offset = 16,					\

	.edge_single_offset = 8,				\
@@ -259,9 +266,8 @@ meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, 
	clear_bit(idx, ctl->channel_map);

}



static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,

				     unsigned int type,

				     u32 *channel_hwirq)

static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,

				    unsigned int type, u32 *channel_hwirq)

{

	u32 val = 0;

	unsigned int idx;
@@ -326,7 +332,7 @@ static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type) 
	u32 *channel_hwirq = irq_data_get_irq_chip_data(data);

	int ret;



	ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);

	ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq);

	if (ret)

		return ret;