Unverified Commit be6bef2a authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export missing Zbc ISA extension 



While Zba and Zbb were exported through hwprobe, Zbc was not. Export it.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-3-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent e45f463a

Documentation/arch/riscv/hwprobe.rst

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@@ -80,6 +80,9 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as

       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.



  * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined

       in version 1.0 of the Bit-Manipulation ISA extensions.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
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@@ -30,6 +30,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZBB		(1 << 4)

#define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)

#define		RISCV_HWPROBE_EXT_ZICBOZ	(1 << 6)

#define		RISCV_HWPROBE_EXT_ZBC		(1 << 7)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_riscv.c

+1 −0
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@@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZBB);

		EXT_KEY(ZBS);

		EXT_KEY(ZICBOZ);

		EXT_KEY(ZBC);

#undef EXT_KEY

	}