Commit be7638a0 authored by Andreas Kemnade's avatar Andreas Kemnade Committed by Stephen Boyd
Browse files

dt-bindings: clock: ti: Convert gate.txt to json-schema 



Convert the OMAP gate clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.
Clean up the examples during conversion to meet modern standards and
remove examples with no additional value.
Due to usage in code and existing devicetree binding, add the
ti,set-rate-parent property.

Signed-off-by: default avatarAndreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20250105170854.408875-2-andreas@kemnade.info


Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent ef94ea4f

Documentation/devicetree/bindings/clock/ti/gate.txt

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Binding for Texas Instruments gate clock.



This binding uses the common clock binding[1]. This clock is

quite much similar to the basic gate-clock [2], however,

it supports a number of additional features. If no register

is provided for this clock, the code assumes that a clockdomain

will be controlled instead and the corresponding hw-ops for

that is used.



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml

[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt



Required properties:

- compatible : shall be one of:

  "ti,gate-clock" - basic gate clock

  "ti,wait-gate-clock" - gate clock which waits until clock is active before

			 returning from clk_enable()

  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling

  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling

  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional

			  clock directly from a clockdomain, see [3] how

			  to map clockdomains properly

  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,

			  required for a hardware errata

  "ti,composite-gate-clock" - composite gate clock, to be part of composite

			      clock

  "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait

				      for clock to be active before returning

				      from clk_enable()

- #clock-cells : from common clock binding; shall be set to 0

- clocks : link to phandle of parent clock

- reg : offset for register controlling adjustable gate, not needed for

	ti,clkdm-gate-clock type



Optional properties:

- clock-output-names : from common clock binding.

- ti,bit-shift : bit shift for programming the clock gate, invalid for

		 ti,clkdm-gate-clock type

- ti,set-bit-to-disable : inverts default gate programming. Setting the bit

  gates the clock and clearing the bit ungates the clock.



Examples:

	mmchs2_fck: mmchs2_fck@48004a00 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&core_96m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <25>;

	};



	uart4_fck_am35xx: uart4_fck_am35xx {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&core_48m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <23>;

	};



	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {

		#clock-cells = <0>;

		compatible = "ti,dss-gate-clock";

		clocks = <&dpll4_m4x2_ck>;

		reg = <0x0e00>;

		ti,bit-shift = <0>;

	};



	emac_ick: emac_ick@4800259c {

		#clock-cells = <0>;

		compatible = "ti,am35xx-gate-clock";

		clocks = <&ipss_ick>;

		reg = <0x059c>;

		ti,bit-shift = <1>;

	};



	emu_src_ck: emu_src_ck {

		#clock-cells = <0>;

		compatible = "ti,clkdm-gate-clock";

		clocks = <&emu_src_mux_ck>;

	};



	dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {

		#clock-cells = <0>;

		compatible = "ti,hsdiv-gate-clock";

		clocks = <&dpll4_m2x2_mul_ck>;

		ti,bit-shift = <0x1b>;

		reg = <0x0d00>;

		ti,set-bit-to-disable;

	};



	vlynq_gate_fck: vlynq_gate_fck {

		#clock-cells = <0>;

		compatible = "ti,composite-gate-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <3>;

		reg = <0x0200>;

	};



	sys_clkout2_src_gate: sys_clkout2_src_gate {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <15>;

		reg = <0x0070>;

	};

Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments gate clock



maintainers:

  - Tero Kristo <kristo@kernel.org>



description: |

  *Deprecated design pattern: one node per clock*



  This clock is quite much similar to the basic gate-clock [1], however,

  it supports a number of additional features. If no register

  is provided for this clock, the code assumes that a clockdomain

  will be controlled instead and the corresponding hw-ops for

  that is used.



  [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml

  [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt



properties:

  compatible:

    enum:

      - ti,gate-clock           # basic gate clock

      - ti,wait-gate-clock      # gate clock which waits until clock is

                                # active before returning from clk_enable()

      - ti,dss-gate-clock       # gate clock with DSS specific hardware

                                # handling

      - ti,am35xx-gate-clock    # gate clock with AM35xx specific hardware

                                # handling

      - ti,clkdm-gate-clock     # clockdomain gate clock, which derives its

                                # functional clock directly from a

                                # clockdomain, see [2] how to map

                                # clockdomains properly

      - ti,hsdiv-gate-clock     # gate clock with OMAP36xx specific hardware

                                # handling, required for a hardware errata

      - ti,composite-gate-clock # composite gate clock, to be part of

                                # composite clock

      - ti,composite-no-wait-gate-clock # composite gate clock that does not

                                        # wait for clock to be active before

                                        # returning from clk_enable()

  "#clock-cells":

    const: 0



  clocks: true



  clock-output-names:

    maxItems: 1



  reg:

    maxItems: 1



  ti,bit-shift:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Number of bits to shift the bit-mask

    maximum: 31

    default: 0



  ti,set-bit-to-disable:

    type: boolean

    description:

      Inverts default gate programming. Setting the bit

      gates the clock and clearing the bit ungates the clock.



  ti,set-rate-parent:

    type: boolean

    description:

      clk_set_rate is propagated to parent clock,



if:

  properties:

    compatible:

      contains:

        const: ti,clkdm-gate-clock

then:

  properties:

    reg: false

  required:

    - compatible

    - "#clock-cells"

    - clocks

else:

  required:

    - compatible

    - "#clock-cells"

    - clocks

    - reg



additionalProperties: false



examples:

  - |

    bus {

      #address-cells = <1>;

      #size-cells = <0>;



      clock-controller@a00 {

        #clock-cells = <0>;

        compatible = "ti,gate-clock";

        clocks = <&core_96m_fck>;

        reg = <0x0a00>;

        ti,bit-shift = <25>;

      };



      clock-controller@d00 {

        compatible = "ti,hsdiv-gate-clock";

        reg = <0x0d00>;

        #clock-cells = <0>;

        clocks = <&dpll4_m2x2_mul_ck>;

        ti,bit-shift = <0x1b>;

        ti,set-bit-to-disable;

      };

    };



  - |

    clock-controller {

      #clock-cells = <0>;

      compatible = "ti,clkdm-gate-clock";

      clocks = <&emu_src_mux_ck>;

    };